TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 46

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

2. VME Interface > VME Slave
46
The address space of the current VME transaction determines how address comparisons are
performed. The following list gives example programming and comparisons for the address
mapping:
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Each slave image has a set of attributes that are used to enable the image and define the
VMEbus transfer characteristics. Each image is has an attribute register (see
on page
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If the VMEbus address is 64-bits, then bits 31 to 0 of the starting address in the Inbound
Translation Starting Address Upper (ITSAUx) register (see
and bits 31 to 16 of the starting address in the Inbound Translation Starting Address
Lower (ITSALx) register (see
address in the Inbound Translation Ending Address Upper (ITEAUx) register (see
Section 10.4.48 on page
Ending Address Lower (ITEALx) register (see
compared against VMEbus address bits 63 to 16.
If the VMEbus address is 32-bits, then bits 31 to 16 of the starting address in the ITSALx
register and bits 31 to 16 of the ending address in the ITEALx register are compared
against VMEbus address bits 31 to 16. The granularity is 64 Kbytes.
If the VMEbus address is 24-bits, then bits 23 to 12 of the starting address in the ITSALx
register and bits 23 to 12 of the ending address in the ITEALx register are compared
against VMEbus address bits 23 to 12. The granularity is 4 Kbytes.
If the VMEbus address is 16-bits, then bits 15 to 4 of the starting address in the ITSALx
register and the bits 15 to 4 of the ending address in the ITEALx register are compared
against VMEbus address bits 15 to 4. The granularity is 16 bytes.
Image enable
Programmable threshold for read-ahead prefetching
Programmable virtual FIFO size for inbound prefetch reads
2eSST slave response rate control: 160, 267, or 320 MB/s
Slave response control: SCT, BLT, MBLT, 2eVME, 2eSST, 2eSST broadcast
Slave address space response control: A16, A24, A32, or A64
Slave response control: VMEbus non-privileged, supervisory, program and data access
cycles
283) with the following fields:
There are no limits imposed on how large an address space a slave image can
represent.
279) and bits 31 to 16 of the ending address in the Translation
Section 10.4.51 on page
Section 10.4.49 on page
Tsi148 PCI/X-to-VME Bus Bridge User Manual
282) and bits 31 to 0 of the ending
Section 10.4.46 on page
80A3020_MA001_13
280), are
Section 10.4.52
277)