TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 93

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

3.3.3
3.3.3.1
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
PCI-X Bus Exception Handling
Tsi148 includes error diagnostic registers which capture information when an error occurs.
The information captured includes the PCI-X bus address, attribute, and command (see
Section 10.4.43 on page
occurs. If another error occurs before software has examined the registers, the information is
not captured and the overflow bit is set.
The following list details the error diagnostic registers in Tsi148:
•
•
•
•
•
For more information on Tsi148 error diagnostic registers, refer to
page
PCI-X Master Exception Handling
The error diagnostic registers are updated when Tsi148 is PCI-X Master and one of the
following errors occurs: the master retry count is exceeded, a split response time-out occurs,
split completion error asserted, or a Master-abort or Target-abort is received.
When the PCI-X Master receives a Master-abort, Target-abort, or the maximum retry count is
exceeded the following steps are taken:
•
•
•
When the PCI-X Master detects a data parity error the following steps are taken:
•
•
•
Error Diagnostic PCI Address Upper (EDPAU)
Error Diagnostic PCI Address Lower (EDPAL)
Error Diagnostic PCI-X Attribute (EDPXA)
Error Diagnostic PCI-X Split Completion Message (EDPXS)
Error Diagnostic PCI Attributes (EDPAT)
Return FF’s on VMEbus with the DTACK signal
Log status information and update PCI-X bus exception registers (see
page
Optional step: generate interrupt
Generate PERR (if enabled)
Log status information and update PCI-X bus exception registers (see
page
Optional step: generate interrupt
272.
272)
272)
The Tsi148 interrupt controller can be programmed to generate an interrupt, when
the exception registers are updated.
272). The error diagnostic registers are updated when the first error
3. PCI/X Interface > PCI-X Mode
Section 10.4.43 on
Section 10.4.43 on
Section 10.4.43 on
93