TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 80

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

3. PCI/X Interface > PCI Mode
3.2.3
3.2.3.1
3.2.3.2
80
PCI Bus Exception Handling
Tsi148 includes error diagnostic registers which capture information when an error occurs.
The information captured includes the PCI bus address and command (see
page
error occurs before software has examined the registers, the information is not captured and
the overflow bit is set.
The following list details the error diagnostic registers in Tsi148:
•
•
•
PCI Master Exception Handling
The error diagnostic registers are updated when Tsi148 is PCI Master and one of the
following errors occurs: the master retry count is exceeded (programmed in the PCI Control /
Status Register, see
When the PCI Master receives a Master-abort, Target-abort, or the maximum count is
exceeded the following steps are taken:
•
•
•
When the PCI Master detects a data parity error the following steps are taken:
•
•
•
PCI Target Exception Handling
The error diagnostic registers are updated when the PCI Target detects an address parity error,
a data parity error, or a delayed transaction time-out occurred.
Error Diagnostic PCI Address Upper (EDPAU)
Error Diagnostic PCI Address Lower (EDPAL)
Error Diagnostic PCI Attributes (EDPAT)
Returns all FFs on VMEbus with the DTACK signal
Log status information and update PCI bus error diagnostic registers
Optional step: generate interrupt
Generate PERR (if enabled)
Log status information and update PCI bus error diagnostic registers
Optional step: generate interrupt
270). The error diagnostic registers are updated when the first error occurs. If another
The Tsi148 interrupt controller can be programmed to generate an interrupt when
the exception registers are updated.
Section 10.4.36 on page
259), a Master-abort or Target-abort is received.
Tsi148 PCI/X-to-VME Bus Bridge User Manual
Section 10.4.41 on
80A3020_MA001_13