TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 35

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

1.3
1.3.1
1.3.1.1
1.3.1.2
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
PCI/X Interface
The Tsi148 PCI/X Interface can operate either in PCI mode or PCI-X mode. The PCI interface
is compliant with the PCI Local Bus Specification (Revision 2.2), while the PCI-X interface is
compliant with the PCI-X Addendum to PCI Local Bus Specification (Revision 1.0b)
The PCI mode can operate at 33 to 66 MHz and has 32-bit/64-bit addressing and data
capability. The PCI-X mode can operate at 50 to 133 MHz and has 32-bit/64-bit addressing
and data capability.
For more information on the PCI/X Interface refer to
PCI/X Target
The PCI and PCI-X targets are described separately in the following sections because they
respond differently to read requests and use different buffering techniques for read
transactions.
PCI Target
Read transactions from the PCI bus are always processed as delayed transactions. The PCI
Target has a 4 Kbyte read buffer, however, in conventional PCI mode a maximum of
512 bytes are used for storing prefetched data. When processing a read request the
requesting PCI bus master is issued a retry from the Tsi148 PCI Target. The read request is
then forwarded to the Linkage Module and then to the Tsi148 VME Master to be serviced.
One delayed read is supported by the PCI Target.
During write transactions, the PCI Target posts write data in its write buffer. The write buffer
consists of a 40 entry command queue and a 4 Kbyte data queue. Tsi148 issues the initiating
PCI bus master immediate acknowledgement upon the write completing. Once the posted
write completes on PCI, Tsi148 obtains the VMEbus and writes the data to the VMEbus
resource independent of the initiating PCI master.
For more information on buffer structure and data flow in Tsi148 refer to
page
Features Not Supported
The following features are not supported by the Tsi148 PCI Target:
— No response to PCI I/O transfers
— PCI/X LOCK_ signal
67.
The term PCI/X refers to functionality that applies to both PCI and PCI-X
operating modes.
Section 3. on page
1. Functional Overview > PCI/X Interface
67.
Section 3. on
35