TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 310

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

10. Registers > Register Map
310
LM2EN (Location Monitor 2 Interrupt Enable): When this bit is high, the location
monitor 2 interrupt is enabled. When the interrupt is enabled, the status bit indicates the state
of the location monitor 2 interrupt. A local bus interrupt is generated if the corresponding
interrupt out bit is set. The interrupt can be polled by setting the enable bit and clearing the
interrupt out bit.
LM1EN (Location Monitor 1 Interrupt Enable): When this bit is high, the location
monitor 1 interrupt is enabled. When the interrupt is enabled, the status bit indicates the state
of the location monitor 1 interrupt. A local bus interrupt is generated if the corresponding
interrupt out bit is set. The interrupt can be polled by setting the enable bit and clearing the
interrupt out bit.
LM0EN (Location Monitor 0 Interrupt Enable): When this bit is high, the location
monitor 0 interrupt is enabled. When the interrupt is enabled, the status bit indicates the state
of the location monitor 0 interrupt. A local bus interrupt is generated if the corresponding
interrupt out bit is set. The interrupt can be polled by setting the enable bit and clearing the
interrupt out bit.
MB3EN (Mail Box 3 Interrupt Enable): When this bit is high, the mail box 3 interrupt is
enabled. When the interrupt is enabled, the status bit indicates the state of the mail box 3
interrupt. A local bus interrupt is generated if the corresponding interrupt out bit is set. The
interrupt can be polled by setting the enable bit and clearing the interrupt out bit.
MB2EN (Mail Box 2 Interrupt Enable): When this bit is high, the mail box 2 interrupt is
enabled. When the interrupt is enabled, the status bit indicates the state of the mail box 2
interrupt. A local bus interrupt is generated if the corresponding interrupt out bit is set. The
interrupt can be polled by setting the enable bit and clearing the interrupt out bit.
MB1EN (Mail Box 1 Interrupt Enable): When this bit is high, the mail box 1 interrupt is
enabled. When the interrupt is enabled, the status bit indicates the state of the mail box 1
interrupt. A local bus interrupt is generated if the corresponding interrupt out bit is set. The
interrupt can be polled by setting the enable bit and clearing the interrupt out bit.
MB0EN (Mail Box 0 Interrupt Enable): When this bit is high, the mail box 0 interrupt is
enabled. When the interrupt is enabled, the status bit indicates the state of the mail box 0
interrupt. A local bus interrupt is generated if the corresponding interrupt out bit is set. The
interrupt can be polled by setting the enable bit and clearing the interrupt out bit.
PERREN (PCI/X Bus Error Interrupt Enable): When this bit is high, the PCI/X bus error
enabled. When the interrupt is enabled, the status bit indicates the state of the PCI/X buss
error interrupt. A local bus interrupt is generated if the corresponding interrupt out bit is set.
The interrupt can be polled by setting the enable bit and clearing the interrupt out bit.
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13