TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 333

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
DON (Done): This read-only field is set if the DMA Controller has successfully completed a
DMA transaction. A successful transaction must meet the following criteria:
1. The DMA Controller has not received any other errors (ERR) between the time the
2. If a commanded abort was issued, then it did not take affect before the transaction was
3. If a commanded pause was issued, then it did not take affect before the transaction was
BSY (Busy): This read-only field reflects the status of the DMA Controller. If set, the DMA
Controller is currently processing a DMA transaction. If cleared, the DMA Controller has
completed a previous transaction and is now idle.
ERRS (Error Source): When the ERR bit is set, this bit indicates the source of the error.
When this bit is set, the PCI/X bus was the source of the error. When this bit is clear, the
VMEbus was the source of the error.
ERT (Error Type): When the ERR bit is set, these bits indicate the type of error received.
Table 141: DSTA ERT Encoding
ERRS
transaction was started and the time that the DMA Controller goes to the idle state.
completed.
completed.
0
0
0
0
1
1
1
1
ERT
00b
01b
10b
11b
00b
01b
10b
11b
Bus error: SCT, BLT, MBLT, 2eVME even data, 2eSST
Bus error: 2eVME odd data
Slave termination: 2eVME even data, 2eSST read
Slave termination: 2eVME odd data, 2eSST read last word
invalid
PCI/X Bus Error
Reserved
Reserved
Reserved
Error Type
10. Registers > Register Map
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