PXB4220E-V33 Infineon Technologies, PXB4220E-V33 Datasheet - Page 102
PXB4220E-V33
Manufacturer Part Number
PXB4220E-V33
Description
IC CHIPSET 8 E1/T1 LINE 256-BGA
Manufacturer
Infineon Technologies
Datasheet
1.PXB4220E-V33.pdf
(290 pages)
Specifications of PXB4220E-V33
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
256-BGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
PXB4220E-V33
PXB4220E-V33IN
PXB4220E-V33IN
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5.1.3.2
In SYM8 mode the framer interface is clocked with an 8.192 MHz clock connected to
RFCLK. The mode is enabled by setting bit om = 10
All timeslots (transmit and receive) will be aligned to each other.
FRCLK[7:0]
FRDAT[7:0]
FRMFB[7:0]
FRFRS[7:0]
FRLOS[7:0]
FTCKO[7:0]
FTDAT[7:0]
FTMFS[7:0]
Data Sheet
Synchronous Mode at 8.192 MHz (SYM8)
Framer Receive Clock
Unused
Framer Receive Data
FRDAT is sampled in the middle of the bit period on the falling
edge of RFCLK
Framer Receive Multiframe Begin
Depending on bits p_ces in pcfN:
0 =
1 =
depending on bit “rfpp” in “opmo”:
0 =
1 =
depending on bit “symn” in “opmo”:
0 =
1 =
FRMFB is always sampled with the opposite clock-edge of
FRDAT.
Framer Receive Frame Synchronization Pulse
Unused
Framer Receive Loss of Signalling
Framer Transmit Clock
Unused
Framer Transmit Data
FTDAT is clocked with the falling edge of RFCLK:
Framer Transmit Multiframe Synchronization
Unused
Structured CES: A pulse on this pin designates the
first frame of a new multiframe
Unstructured CES: Unused
FRMFB is active low
FRMFB is active high
FRMFB[0] is used for frame and multiframe
synchronization in receive and transmit direction of
all ports. FRMFB[1:7] are unused
FRMFB[N] is used for frame and multiframe
synchronization in receive and transmit direction of
corresponding ports
102
PXB 4219E, PXB 4220E, PXB 4221E
B
in “opmo”, see
Interface Description
Chapter 7.24
IWE8, V3.4
2003-01-20
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