PXB4220E-V33 Infineon Technologies, PXB4220E-V33 Datasheet - Page 105

IC CHIPSET 8 E1/T1 LINE 256-BGA

PXB4220E-V33

Manufacturer Part Number
PXB4220E-V33
Description
IC CHIPSET 8 E1/T1 LINE 256-BGA
Manufacturer
Infineon Technologies
Datasheet

Specifications of PXB4220E-V33

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
256-BGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
PXB4220E-V33
PXB4220E-V33IN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PXB4220E-V33
Manufacturer:
Intel
Quantity:
10
Part Number:
PXB4220E-V33
Manufacturer:
Infineon Technologies
Quantity:
10 000
5.2
Figure 29
The UTOPIA receive and transmit interfaces are implemented according to the ATM
forum UTOPIA Level 2 Specification [6] and to the UTOPIA Level 1 Specification [5].
For UTOPIA level 2 compliant mode, the device is compatible to a PHY layer with 8 data
lines and 5 address lines.
In UTOPIA level 1 compliant mode the interface can be configured to ATM and PHY
layer with 8 data lines. In this case the address lines should be left unconnected.
According to the UTOPIA standard the ATM-Layer polls the PHY-Ports via the UTOPIA
address lines. If the address matches the programmed address range, the PHY controls
the flow of data via the TXCLAV or RXCLAV signal.
In transmit direction the PHY indicates via assertion of TXCLAV whether the
corresponding port is capable of accepting data. In case data can not be transferred to
the addressed port due to overrun of the programmed threshold of the port-specific cell
buffer, the TXCLAV won’t be activated.
In receive direction, RXCLAV is activated, if data is available at the addressed port.
Depending on the value of the “utmaster” bit in the “UTOPIA Configuration Register”
(“utconf”, see
or PHY-Layer (slave mode). As an ATM-Layer, the IWE8 can only work in UTOPIA level
1 compliant mode. As PHY Layer, IWE8 supports both, single PHY in UTOPIA level 1
compliant mode and single/multi PHY in UTOPIA level 2 compliant mode. The selection
between UTOPIA level 1 and level 2 can be done via the “utlevel” bit in “utconf”.
5.2.1
The device can implement up to 8 PHY-Ports (= framer ports).
Data Sheet
UTOPIA Interface
Port Addresses
Chapter
UTOPIA Receive and Transmit Interfaces in Slave Mode
7.34) the IWE8 will either act as an ATM -Layer (master mode)
IWE8
RXADR[0-4]
RXDAT[0-7]
TXADR[0-4]
TXDAT[0-7]
RXCLAV
TXCLAV
RXSOC
RXENB
TXSOC
RXPTY
RXCLK
TXENB
TXPTY
TXCLK
105
PXB 4219E, PXB 4220E, PXB 4221E
UTOPIA
Transmit
Interface
(Level 2)
UTOPIA
Receive
Interface
(Level 2)
Interface Description
IWE8, V3.4
2003-01-20
Urati

Related parts for PXB4220E-V33