PXB4220E-V33 Infineon Technologies, PXB4220E-V33 Datasheet - Page 78

IC CHIPSET 8 E1/T1 LINE 256-BGA

PXB4220E-V33

Manufacturer Part Number
PXB4220E-V33
Description
IC CHIPSET 8 E1/T1 LINE 256-BGA
Manufacturer
Infineon Technologies
Datasheet

Specifications of PXB4220E-V33

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
256-BGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
PXB4220E-V33
PXB4220E-V33IN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PXB4220E-V33
Manufacturer:
Intel
Quantity:
10
Part Number:
PXB4220E-V33
Manufacturer:
Infineon Technologies
Quantity:
10 000
IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Operational Description
During this lock-in process, the output frequency might temporarily reach the
programmed minimum or maximum value. This strongly depends on the initial difference
of the data buffer filling from the value given by “avbN”.
As re-initialization of the data buffer is not reported to the ICRC, PLL-ACM will detect a
huge difference between data buffer filling and the value given by “avbN”. As a result the
output frequency will be driven to it's lowest allowed value and stays there for a relative
long period of time. For this reason it is important to program the field “tur” in register
“condN” with the smallest possible value.
4.5.11.4 SRTS with ACM:
The combination of SRTS and ACM is used when the derived network clock of the SRTS
generator differs from the derived network clock of the SRTS receiver. The maximum
difference is relatively small (+/-4.6 ppm) and should be compensated by ACM. In this
case the shifting of the difference between ACM data and register “avbN”, as
programmed in register “asfN”, has to be reduced. Stable operation of PLL-ACM in
parallel with PLL-SRTS can not be guaranteed if the shifting is not reduced. The cut off
frequency of PLL-ACM has to be much lower than the cut off frequency of PLL-SRTS,
as these PLLs are working in parallel in this case. This will also reduce the effects of
CDV, because the cut off frequency of PLL-ACM is reduced. The tuning range (register
“condN”, field “tur”) can not be reduced as PLL-ACM has to compensate jitter which is
generated by or passed through PLL-SRTS.
Data Sheet
78
2003-01-20

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