PXB4220E-V33 Infineon Technologies, PXB4220E-V33 Datasheet - Page 132
PXB4220E-V33
Manufacturer Part Number
PXB4220E-V33
Description
IC CHIPSET 8 E1/T1 LINE 256-BGA
Manufacturer
Infineon Technologies
Datasheet
1.PXB4220E-V33.pdf
(290 pages)
Specifications of PXB4220E-V33
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
256-BGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
PXB4220E-V33
PXB4220E-V33IN
PXB4220E-V33IN
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Intel
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channel_
mode
ref_slot
1)
2)
Note: To allow IWE8 internal initialization, all channels must remain in inactive mode for
Note: If frame based SDT without CAS is used and filling level
6.1.2.4
Read/write Address 00400
Reset value: Not applicable. RAM must be reset and initialized via SW.
Data Sheet
Not used
non-P format, cell may have only 46 user data octets in P format
Cb: Required bytes for the CAS sub-block in an ATM cell
31
23
15
7
at least 250 s after activation of the port (i.e. setting pcfN[p_rx_act] = 1). During
this time the device connected to the Framer Transmit Interface has to be in
normal operation.
band_width
Multiframe based SDT without CAS should not be used.
RAM2: AAL Transmit Continuation Slot
Not used
X =
0 =
1 =
Channel mode
00 =
01 =
10 =
11 =
Reference slot indicator
1 =
next_slot_nr[4:0]
part_fill has to be fulfilled for correct operation.
If pcfN[p_ces] = 1 or [aal0] = 1
Disabled
Enabled
Inactive mode
Active mode (normal mode)
Standby mode
Active mode (normal mode)
This slot is a reference slot
H
to 005FF
ref_slot_nr[4:0]
Not used
H
132
PXB 4219E, PXB 4220E, PXB 4221E
slot_index[4:0]
cont_slot
Not used
Memory Structure
= 1
45, the condition
IWE8, V3.4
2003-01-20
ref_slot
= 0
24
16
8
0
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