PXB4220E-V33 Infineon Technologies, PXB4220E-V33 Datasheet - Page 274

• Manufacturer Part Number: PXB4220E-V33
• Description: IC CHIPSET 8 E1/T1 LINE 256-BGA
• Manufacturer: Infineon Technologies

Specifications of PXB4220E-V33

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: PXB4220E-V33; PXB4220E-V33IN

12
12.1
The ATM Adaptation Layer 1 (AAL1) consists of two sublayers: The Segmentation and
Reassembly Sublayer (SAR), which is responsible for sequence integrity of the
transmitted ATM cell stream and the Convergency Sublayer, responsible for blocking of
user data into 47-octet SAR boundaries.
Figure 74
[31].
Figure 74
Data Sheet
Pointer
CSI
SC
CRC
Py
SN
SNP
SAR
SDU
PDU
CSI
1 bit
ATM Header
SC
3 bit
= octet offset of data block over 2 cells (111 1111 if not required)
= Convergency Sublayer Indication
= Sequence Count
= Cyclic Redundancy Check
= Even Parity bit
= Sequence Number incremented by 1 modulo 8 for each SAR-SDU
= Sequence Number Protection
= Segmentation & Reassembly
= Service Data Unit
= Protocol Data Unit
Non-P Format: CSI = 0
P format:
5 octets
gives an overview on the AAL1 frame-structure as defined in ITU-T I.363.1
Appendix
ATM Adaptation Layer 1
Structure of the AAL1 SAR-PDU
CRC
3 bit
SN
CSI = 1 if SC = 0,2,4 or 6, P-field may be inserted
CSI = 0 if SC = 1,3,5 or 7, P-field is unused (Non-P format used)
1 octet
1 bit
Py
SNP
Non-P format
Parity
1 bit
P format
ATM-SDU = SAR-PDU
Pointer
7 bit
1 octet
P
48 octets
274
SAR-SDU
47 octets
PXB 4219E, PXB 4220E, PXB 4221E
User information
AAL user info
User information
N octets
47 octets
46 octets
Dummy Fill
CS-Sublayer
SAR-Sublayer
ATM Layer
IWE8, V3.4
Appendix
2003-01-20
Aal1