M69030 Asiliant Technologies, M69030 Datasheet - Page 100

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

8-12
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69030 Databook
For the AR and DAC sub-indexed register groups:
Note: Write access to the indices for these two sub-indexed register groups must
be enabled using these 2 bits of this register, since these indices are controlled in
the same way as the actual sub-indexed registers of these groups.
1 0
0 0
0 1
1 0
1 1
Bit
General Control and Status Registers
All write access from the I/O space to these sub-indexed
register groups of both pipelines is disabled.
The AR and DAC sub-indexed register groups that belong
to pipeline A are made writable from the I/O space using
pipeline A’s indices for these register groups. Neither the
AR or DAC sub-indexed register groups that belong to
pipeline B, or their indices, are writable from the I/O space.
If bit 1 of pipeline A’s shadow of XR09 is set to 0, then the
index register for pipeline A’s AR register group (ARX) tog-
gles between being an index and a data port when written
to, and reading from pipeline A’s shadow of ST01 sets
ARX to being an index.
If bit 1 of pipeline A’s shadow of XR09 is set to 1, then the
index register for pipeline A’s AR register group (ARX) re-
mains locked as being only an index register.
The AR and DAC sub-indexed register groups that belong
to pipeline B are made writable from the I/O space using
pipeline B’s indices for these register groups. Neither the
AR or DAC sub-indexed register groups that belong to
pipeline A, or their indices, are writable from the I/O space.
If bit 1 of pipeline B’s shadow of XR09 is set to 0, then the
index register for pipeline A’s AR register group (ARX) tog-
gles between being an index and a data port when written
to, and reading from pipeline B’s shadow of ST01 sets
ARX to being an index.
If bit 1 of pipeline A’s shadow of XR09 is set to 1, then the
index register for pipeline A’s AR register group (ARX) re-
mains locked as being only an index register.
Write access from the I/O space to the AR and DAC sub-
indexed register groups of both pipelines is enabled.
For whichever pipeline wherein bit 1 of XR09 is set to 0,
the index register for that pipeline’s AR register group
(ARX) toggles between being an index and a data port
when written to, and reading from EITHER pipeline’s shad-
ow of ST01 will set it to being an index.
For whichever pipeline wherein bit 0 of XR09 is set to 1,
the index register for that pipeline’s AR register group
(ARX) remains locked as being only an index register.
Effect on Write Accesses to AR and
DAC Sub-indexed Register Groups
Revision 1.3 11/24/99