M69030 Asiliant Technologies, M69030 Datasheet - Page 169

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

AR10
read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 10h
shadowed for pipelines A and B
7
6
5
4
3
`efmp
A
B
Palette Bits
Palette Bits

P5, P4
P5, P4
Select
Select
Palette Bits P5, P4 Select
Pixel Width/Clock Select
Pixel Panning Compatibility
Reserved
Enable Blinking/Select Background Intensity
69030 Databook
7
Mode Control Register
0: P5 and P4 for each of the 16 selected colors (for modes that use 16 colors) are
individually provided by bits 5 and 4 of their corresponding Palette Registers (AR00-0F).
1: P5 and P4 for all 16 of the selected colors (for modes that use 16 colors) are provided
by bits 1 and 0 of Color Select Register (AR14).
0: Six bits of video data (translated from 4 bits via the palette) are output every dot clock.
1: Two sets of 4 bits of data are assembled to generate 8 bits of video data which is output
every other dot clock, and the Palette Registers (AR00-0F) are bypassed.
Note: This bit is set to 0 for all of the standard VGA modes, except mode 13h.
0: Scroll both the upper and lower screen regions horizontally as specified in the Horizontal
Pixel Panning Register (AR13).
1: Scroll only the upper screen region horizontally as specified in the Horizontal Pixel
Panning Register (AR13).
Note: This bit has application only when split-screen mode is being used, where the
display area is divided into distinct upper and lower regions which function somewhat like
separate displays.
0: Disables blinking in graphics modes and, in text modes, sets bit 7 of the character
attribute bytes to control background intensity, instead of blinking.
1: Enables blinking in graphics modes and, in text modes, sets bit 7 of the character
attribute bytes to control blinking, instead of background intensity.
Note: The blinking rate is derived by dividing the VSYNC signal. The Blink Rate Control
Register (FR19) defines the blinking rate.
Pixel Width/
Pixel Width/
Clk Select
Clk Select
6
Panning
Panning
Compat
Compat
Pixel
Pixel
5
Attribute Controller Registers
Reserved
Reserved
4
Bkgnd Int
Bkgnd Int
En Blink/
En Blink/
Select
Select
3
Char Code
Char Code
En Line Gr
En Line Gr
2
Display
Display
Select
Select
Revision 1.3 11/24/99
Type
Type
1
Alpha Mode
Alpha Mode
Graphics/
Graphics/
0
12-3