M69030 Asiliant Technologies, M69030 Datasheet - Page 254

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M69030

Manufacturer Part Number
M69030
Description
Manufacturer
Asiliant Technologies
Datasheet

Specifications of M69030

Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed

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15-16
FR10
read/write at I/O address 3D1h with index at I/O address 3D0h set to 10h
shadowed only for pipeline A
7
6-4
.
`efmp
A
B
[6-4]
[6-4]
Bits
Bits
Bits
[6-4]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
4-bit pack color STN-DD w/frame accel.
Monochrome STN-DD w/o frame accel.
Reserved
(R/W)
Reserved (R/W) (reset state: 0)
Shift Clock Divide (reset state: 000)
69030 Databook
(0)
7
FP Format 0 Register
SHFCLK
SHFCLK
SHFCLK
DCLK/2
DCLK/2
DCLK/4
DCLK/8
DCLK/2
DCLK
DCLK
DCLK
These bits specify the frequency ratio between the internal dot clock (DCLK) and flat panel
shift clock (SHFCLK) signal.
Color TFT
6
SHFCLK
SHFCLK
SHFCLK
Pixel /
Pixel /
Pixel /
2 2/3
5 1/3
Shift Clock Divide
1
2
1
2
4
8
(000)
5
Max bpp
Max bpp
Max bpp
24
12
16
16
2
4
8
8
not shadowed for this pipeline
Flat Panel Registers
4
3
Mono / Color
[6-4]
[6-4]
Bits
[6-4]
Bits
4-bit pack color STN-DD w/o frame accel.
Bits
000
010
000
100
000
010
001
011
100
101
110
111
001
010
011
101
110
111
001
011
100
101
110
111
Monochrome STN-DD w/o frame accel.
(00)
4-bit pack Color STN-SS
SHFCLK
SHFCLK
DCLK/16
SHFCLK
DCLK/2
DCLK/4
DCLK/2
DCLK/4
DCLK/8
DCLK/2
DCLK/4
DCLK
2
SHFCLK
SHFCLK
SHFCLK
Revision 1.3 11/24/99
Pixel /
Pixel /
Pixel /
1 1/3
2 2/3
5 1/3
2 2/3
5 1/3
1
16
2
4
8
Panel Type
(00)
Max bpp
Max bpp
Max bpp
16
16
16
0
4
8
2
4
8
8

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