M69030 Asiliant Technologies, M69030 Datasheet - Page 77

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

DEVCTL
read/write at PCI configuration offset 04h
byte or word accessible
accessible only via PCI configuration cycles
15-10
9
8
7
6
`efmp
15

Reserved
Fast Back-to-Back Enable for Masters
SERR# Enable
Wait Cycle Control
Parity Error Response
69030 Databook
14
13
Reserved
(0000:00)
Each of these bits always return a value of 0 when read.
This bit applies only to PCI Bus masters. Since this graphics controller never functions as
a PCI Bus master, this bit always returns a value of 0 when read.
0: Disables the use of SERR# and the setting of bit 14 (Signaled System Error bit) in the
Device Status Register (DEVSTAT) to 1 as a response to an address parity error. This is
the default after reset.
1: Enables the use of SERR# and the setting of bit 14 (Signaled System Error bit) in the
Device Status Register (DEVSTAT) to 1 as a response to an address parity error.
This bit controls enables and disables address stepping. Since this graphics controller
always supports address stepping, this bit always returns a value of 1 when read.
0: Disables the use of PERR# as a response to detecting either data or address parity
errors. Disables the setting of bit 14 (Signaled System Error bit) in the Device Status
Register (DEVSTAT) to 1 as a response to an address parity error. This is the default after
reset.
1: Enables the use of PERR# as a response to detecting either data or address parity
errors. Enables the setting of bit 14 (Signaled System Error bit) in the Device Status
Register (DEVSTAT) to 1 as a response to an address parity error.
Note: Bit 8 (SERR# Enable) of this register must also be set to 1 to enable the use of
SERR# and the setting of bit 14 (Signaled System Error bit) in the Device Status Register
(DEVSTAT) to 1 as a response to an address parity error.
Device Control Register
12
11
10
PCI Configuration Registers
Bk-Bk
Fast
(0)
9
SERR
Enbl
(0)
8
Wait
Cycl
Ctl
(1)
7
PERR
Enbl
(0)
6
Snoop
VGA
Pal
(0)
5
Inval.
Mem
Wrt /
(0)
4
Spec
Cycl
(0)
3
Revision 1.3 11/24/99
Mstr
Bus
(0)
2
Mem
Acc
(0)
1
Acc
I/O
(0)
0
7-3