M69030 Asiliant Technologies, M69030 Datasheet - Page 107

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

CR03
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 03h
shadowed for pipelines A and B
7
6-5
4-0
`efmp
A
B
Reserved
Reserved

Reserved
Display Enable Skew Control
Horizontal Blanking End Bits 4-0
69030 Databook
7
Horizontal Blanking End Register
Values written to this bit are ignored. To maintain consistency with the VGA standard, a
value of 1 is returned whenever this bit is read. At one time, this bit was used to enable
access to certain light pen registers. At that time, setting this bit to 0 provided this access,
but setting this bit to 1 was necessary for normal operation.
Defines the degree to which the start and end of the active display area are delayed along
the length of a scanline to compensate for internal pipeline delays.
These 2 bits describe the delay in terms of a number character clocks.
These 5 bits provide the 5 least significant bits of either a 6-bit or 8-bit value that specifies
the end of the blanking period relative to its beginning on a single scanline.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the
horizontal blanking end is specified with a 6-bit value. The 5 least significant bits of the
horizontal blanking end are supplied by these 5 bits of this register, and the most significant
bits is supplied by bit 7 of the Horizontal Sync End Register (CR05).
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the horizontal
blanking end is specified with an 8-bit value. The 5 least significant bits of the horizontal
blanking end are supplied by these 5 bits of this register, the next most significant bit is
supplied by bit 7 of the Horizontal Sync End Register (CR05), and the 2 most significant
bits are supplied by bits 7 and 6 of the Extended Horizontal Blanking End Register (CR3C).
This 6-bit or 8-bit value should be programmed to be equal to the least significant 6 or 8
bits, respectively, of the result of adding the length of the blanking period in terms of
character clocks to the value specified in the Horizontal Blanking Start Register (CR02).
Display Enable Skew
Display Enable Skew
6
Control
Control
6 5
0 0
0 1
1 0
1 1
Bit
5
CRT Controller Registers
no delay
delayed by 1 character clock
delayed by 2 character clocks
delayed by 3 character clocks
4
Amount of Delay
Horizontal Blanking End Bits 4-0
Horizontal Blanking End Bits 4-0
3
2
Revision 1.3 11/24/99
1
0
9-5