M69030 Asiliant Technologies, M69030 Datasheet - Page 29

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

B69030 and M69030 PCI/AGP Bus Interface
Note:
driven high for one clock before released, and are not driven for at least one cycle after being released by
the previous device. A pull-up provided by the bus controller is used to maintain an inactive level between
transactions.
`efmp
BGA
Pin
M1
C1
D2
K2
K1
K4
L1

mBGA
S/TS stands for “Sustained Tri-state”. These signals are driven by only one device at a time, are
69030 Databook
Pin
C1
H3
H1
H2
E4
J2
J1
Pin Name
BUSCLK
FRAME#
RESET#
TRDY#
STOP#
IRDY#
PAR
Type
S/TS
S/TS
I/O
In
In
In
In
Active Powered
High
High
Low
Low
Low
Low
Low
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
Pin Descriptions
Reset. This input sets all signals and registers in the chip
to a known state. All outputs from the chip are tri-stated or
driven to an inactive state. If STNDBY# and RESET# are
active at the same time, RESET# only initializes the
ENAVDD, ENAVEE and ENABKL on pin 3. The rest of
the logic on the chip does not receive the reset signal
and will remain uninitialized.
Bus Clock. This input provides the timing reference for all
PCI and AGP bus transactions. All bus inputs except
RESET# are sampled on the rising edge of BUSCLK.
BUSCLK may be any frequency from DC up to 33MHz for
PCI, or up to 66MHz for AGP.
Parity. This signal is used to maintain even parity across
AD0-31 and C/BE0-3#. PAR is stable and valid one clock
after the address phase. For data phases PAR is stable
and valid one clock after either IRDY# is asserted on a
write transaction or TRDY# is asserted on a read
transaction. Once PAR is valid, it remains valid until one
clock after the completion of the current data phase (i.e.,
PAR has the same timing as AD0-31 but delayed by one
clock). The bus master drives PAR for address and write
data phases; the target drives PAR for read data phases.
Cycle Frame. Driven by the current master to indicate the
beginning and duration of an access. Assertion indicates
a bus transaction is beginning (while asserted, data
transfers continue); de-assertion indicates the transaction
is in the final data phase
Initiator Ready. Indicates the bus master's ability to
complete the current data phase of the transaction. During
a write, IRDY# indicates valid data is present on AD0-31;
during a read it indicates the master is prepared to accept
data. A data phase is completed on any clock when both
IRDY# and TRDY# are sampled then asserted (wait cycles
are inserted until this occurs).
Target Ready. Indicates the target's ability to complete the
current data phase of the transaction. During a read,
TRDY# indicates that valid data is present on AD0-31;
during a write it indicates the target is prepared to accept
data. A data phase is completed on any clock when both
IRDY# and TRDY# are sampled then asserted (wait cycles
are inserted until this occurs).
Stop. Indicates the current target is requesting the master
to stop the current transaction.
Description
Revision 1.3 11/24/99
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