M69030 Asiliant Technologies, M69030 Datasheet - Page 101

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

MSS
read/write at I/O address 3CBh
shared by both pipelines A and B
7-4
3
2
1
0
`efmp
A
&
B

Reserved
Memory Space Shadowing Enable
Pipeline A or B Register Read Select
Pipeline A Register Write Enable
Pipeline B Register Write Enable
69030 Databook
7
Memory Space Shadowing Register
These bits always return the value of 0 when read.
0: Disables memory space shadowing. All registers for pipeline A remain mapped to mem-
ory offsets 400000 through 7FFFFF. All registers for pipeline B remain mapped to memory
offsets C00000 through FFFFFF. This is the default after reset.
1: Enables memory space shadowing. All shadows of all registers for either pipeline A or
B (not both at the same time) are accessible at both memory offsets 400000 through
7FFFFF and C00000 through FFFFFF. The choice of which pipeline’s registers are to be
made accessible for reading or writing is controlled via bits 2 through 0 of this register.
Note: This bit has no effect if bit 3 of this register is set to 0.
0: If bit 3 of this register is set to 1, then the registers belonging to or shared by pipeline A
are accessible for reading via both memory offsets 400000 through 7FFFFF and C00000
through FFFFFF, and those registers belonging exclusively to pipeline B are not. This is
the default after reset.
1: If bit 3 of this register is set to 1, then the registers belonging to or shared by pipeline B
are accessible for reading via both memory offsets 400000 through 7FFFFF and C00000
through FFFFFF, and those registers belonging exclusively to pipeline A are not.
Note: This bit has no effect if bit 3 of this register is set to 0.
0: If bit 3 of this register is set to 1, then the registers belonging exclusively to pipeline A
are NOT accessible for writing via either memory offsets 400000 through 7FFFFF or
C00000 through FFFFFF. This is the default after reset.
1: If bit 3 of this register is set to 1, then the registers belonging to or shared by pipeline A
are accessible for writing via memory offsets 400000 through 7FFFFF.
Note: This bit has no effect if bit 3 of this register is set to 0.
0: If bit 3 of this register is set to 1, then the registers belonging exclusively to pipeline B
are NOT accessible for writing via either memory offsets 400000 through 7FFFFF or
C00000 through FFFFFF. This is the default after reset.
1: If bit 3 of this register is set to 1, then the registers belonging to or shared by pipeline B
are accessible for writing via memory offsets C00000 through FFFFFF.
6
Reserved
(0000)
General Control and Status Registers
5
4
Mem Shad
En
(0)
3
A/B Reg
Read
(0)
2
Pipe A Reg
Revision 1.3 11/24/99
Write
(0)
1
Pipe B Reg
Write
(0)
0
8-13