M69030 Asiliant Technologies, M69030 Datasheet - Page 34

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

2-10
B69030 and M69030 Flat Panel Display Interface (continued)
Notes:
To accommodate a wide variety of panel types, the graphics controller has been designed to output its data
in any of a number of formats. These formats include different data widths for the colors belonging to each
pixel, and the ability to accommodate different pixel data transfer timing requirements.
For STN-DD panels, pins P0 through P35 are organized into groups corresponding to the upper and lower
parts of the panel. The names of the signals for the upper and lower parts follow a naming convention of
Uxx and Lxx, respectively.
For panels that require a pair of adjacent pixels be sent with every shift clock, pins P0 through P35 are
organized into groups corresponding to the first and second (from right to left) pixels of each pair of pixels
being sent. The names of the signals for the first and second pixels of each such pair follow a naming
convention of Fxx and Sxx, respectively.
Panels that transfer data on both edges of SHFCLK are also supported. See the description for register
FR12 for more details.
Signals mapping for 18 bit TFT Panels:
B0-B5 should match P2-P7, G0-G5 should match P10-P15, R0-R5 should match P18-P23.
`efmp
BGA
Pin
W5
W4
Y5
Y4
V6
V5
U6

mBGA
69030 Databook
Pin
M6
P5
N5
R4
T4
L7
T3
LP (CL1)(DE) (BLANK#) OUT
ENAVEE (ENABKL)
M (DE) (BLANK#)
Pin Name
ENAVDD
SHFCLK
ENABKL
FLM
Type Active Powered
OUT
OUT
OUT
I/O
I/O
I/O
Pin Descriptions
High
High
High
High
High
High
High
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
Shift Clock. Pixel clock for flat panel data.
First Line Marker. Flat Panel equivalent of
VSYNC.
Latch Pulse. Flat Panel equivalent of HSYNC.
May also be configured as Display Enable (DE)
or BLANK#. Some panels use the signal name
of CL1.
M signal for panel AC drive control (may also
be called ACDCLK). May also be configured
as BLANK# or as Display Enable (DE) for TFT
Panels.
Power sequencing control for panel driver
electronics voltage VDD.
Power sequencing control for panel bias
voltage VEE. May also be configured as
ENABKL.
Power sequencing control for enabling the
backlight.
Description
Revision 1.3 11/24/99