M69030 Asiliant Technologies, M69030 Datasheet - Page 299
M69030
Manufacturer Part Number
M69030
Description
Manufacturer
Asiliant Technologies
Datasheet
1.M69030.pdf
(387 pages)
Specifications of M69030
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Quantity
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Part Number:
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CHIPS
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M69030P
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MIT
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MR20/A0
read/write at I/O address 3D3h with index at address 3D2h set to 20h/A0h
shared & shadowed for each playback engine at MR20, and cross-shared for the other at MRA0
7
6
5
4
3
2
1-0
`efmp
PB
PB
1
2
Vert. Autoctr
Vert. Autoctr
Playback
Playback
Enable
Enable
Playback Vertical Auto-Centering Enable
Playback Width Source
Playback Pointer Select 1
CPU Double Buffer Flag
Playback Pointer Select 2
Double Buffer Trigger
Reserved
69030 Databook
7
0: Allow software to employ a delay to properly center the playback window vertically. This
is done usually via bit 4 of the Pixel Pipeline Configuration Register 1 (XR81).
1: Activate a hardware-based auto-centering mechanism.
0: Uses MR28 for Playback width
1: Uses MR34 for Playback width
0: The pointer to the location in the frame buffer from which frames/fields of video data are
played back is selected by bit 4 of this register.
1: The pointer to the location in the frame buffer from which frames/fields of video data are
played back is controlled by bit 3 of this register.
0: Playback memory address PTR1
1: Playback memory address PTR2
0: The pointer to the location in the frame buffer from which frames/fields of video data are
played back is selected by bit 4 of this register.
1: The pointer to the location in the frame buffer from which frames/fields of video data are
played back toggles between the addresses indicated by PTR1 and PTR2 after each frame/
field captured.
0: Retains old PTR.
1: Takes new PTR on next VSYNC if bit 5 is set to 1.
0
0
5
1
1
1
1
Playback
Playback
Source
Source
Playback Control 3 Register
Width
Width
Bit
0
1
4
0
0
1
1
6
3
X
X
0
1
0
1
Selects playback memory pointer address 1
Selects playback memory pointer address 2
Selects playback memory pointer address 1
Pointer to the location from which frames/fields of data are read toggles between
addresses indicated by PTR1and PTR2 after each frame/field captured
Selects playback memory pointer address 2
Pointer to the location from which frames/fields of data are read toggles between
addresses indicated by PTR1and PTR2 after each frame/field captured
Playback
Playback
Pointer
Pointer
Select
Select
5
Multimedia Registers
CPU Double
CPU Double
Buffer Flag
Buffer Flag
4
Playback Pointer Select
Playback
Playback
Select 2
Select 2
Pointer
Pointer
3
Double
Trigger
Double
Trigger
Buffer
Buffer
2
Revision 1.3 11/24/99
1
Reserved
Reserved
0
16-17
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