XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet

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XCB56362PV100

Manufacturer Part Number
XCB56362PV100
Description
DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XCB56362PV100

Package
144LQFP
Numeric And Arithmetic Format
Floating-Point
Maximum Speed
100 MHz
Ram Size
33 KB
Device Million Instructions Per Second
100 MIPS

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Freescale Semiconductor
Technical Data
DSP56362
24-Bit Audio Digital Signal Processor
1
Freescale Semiconductor, Inc. designed the DSP56362
to support digital audio applications requiring digital
audio compression and decompression, sound field
processing, acoustic equalization, and other digital audio
algorithms. The DSP56362 uses the high performance,
single-clock-per-cycle DSP56300 core family of
programmable CMOS digital signal processors (DSPs)
combined with the audio signal processing capability of
the Freescale Symphony™ DSP family, as shown in
Figure
increase over Freescale’s popular Symphony family of
DSPs while retaining code compatibility. Significant
architectural enhancements include a barrel shifter,
24-bit addressing, instruction cache, and direct memory
access (DMA). The DSP56362 offers 100 million
instructions per second (MIPS) using an internal 100
MHz clock at 3.3 V.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
1-1. This design provides a two-fold performance
Overview
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2 Signal/Connection Descriptions . . . . . . . . . 2-1
3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . 3-1
4 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
5 Design Considerations . . . . . . . . . . . . . . . . 5-1
6 Ordering Information . . . . . . . . . . . . . . . . . . 6-1
A Power Consumption Benchmark . . . . . . . . A-1
B IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Document Number: DSP56362
Rev. 4, 08/2006

XCB56362PV100 Summary of contents

Page 1

... The DSP56362 offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V. This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. Document Number: DSP56362 Rev. 4, 08/2006 Contents 1 Overview ...

Page 2

... Memory ROM 24 6144 × Expansion ROM Area 24 6144 × External Address Bus Address Switch DRAM/SRAM Bus 11 Interface & Control I - Cache Control External 24 Data Bus Switch Data Power Mngmnt. Data ALU 6 JTAG OnCE™ 56-bit Barrel Shifter AA0456G Freescale Semiconductor ...

Page 3

... Phase-locked loop (PLL) – Software programmable PLL-based frequency synthesizer for the core clock – Allows change of low-power divide factor (DF) without loss of lock – Output clock with skew elimination — Hardware debugging support Freescale Semiconductor DSP56362 Technical Data, Rev. 4 Overview 1-3 ...

Page 4

... DSP56362 Technical Data, Rev Data RAM Size Y Data RAM Size 5632 × 24-bit 5632 × 24-bit 5632 × 24-bit 5632 × 24-bit 5632 × 24-bit 3584 × 24-bit 5632 × 24-bit 3584 × 24-bit Freescale Semiconductor ...

Page 5

... Document Name DSP56300 Family Manual DSP56362 User’s Manual DSP56362 Product Brief DSP56362 Data Sheet (this document) Freescale Semiconductor Table 1-1 DSP56362 Documentation Description Detailed description of the 56000-family architecture and the 24-bit core processor and instruction set Detailed description of memory, peripherals, and ...

Page 6

... Overview 1-6 NOTES DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 7

... Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals. 3 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. 4 Port D signals are the GPIO port signals which are multiplexed with the DAX signals. Freescale Semiconductor 2-1. 1 Port A 2 ...

Page 8

... PB13 Double DS HRD/HRD PB11 HWR/HWR PB12 Double HR HTRQ/HTRQ PB14 HRRQ/HRRQ PB15 Mode HA0 HA2 SDA SCL HREQ Port C GPIO PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 Port D GPIO PD0 PD1 Timer GPIO TIO0 AA0601 Freescale Semiconductor ...

Page 9

... SHI, ESAI, DAX, and Timer Power—V CCS I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two V Freescale Semiconductor Table 2-2 Power Inputs Description is V dedicated for PLL use. The voltage should be well-regulated and the ...

Page 10

... If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. CLKOUT is not functional at frequencies of 100 MHz and above. DSP56362 Technical Data, Rev 0.47 µF capacitor P connection. P connection. P1 connections. S Freescale Semiconductor ...

Page 11

... Type State during Reset D0–D23 Input/Output Freescale Semiconductor PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal the PLL is not used, PCAP may be tied to V PLL Initial/Non maskable Interrupt—During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled ...

Page 12

... TA can operate synchronously or asynchronously, depending on the setting of the TAS bit in the operating mode register (OMR). TA functionality may not be used while performing DRAM type accesses, otherwise improper operation may result. DSP56362 Technical Data, Rev. 4 Signal Description Freescale Semiconductor ...

Page 13

... Input Ignored Input BB Input/ Input Output Freescale Semiconductor External Memory Expansion Port (Port A) Signal Description Bus Request— active-low output, never tri-stated asserted when the DSP requests bus mastership deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP56362 is a bus master or a bus slave. Bus “ ...

Page 14

... MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQC is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQC to exit the wait state. This input tolerant. DSP56362 Technical Data, Rev. 4 Signal Description Freescale Semiconductor ...

Page 15

... HDI08 port control register (HPCR). See 6.5.6 Host Port Control Register (HPCR) on page Section 6-13 for detailed descriptions of this register and (See Host Interface (HDI08) on page Section 6-1.) for descriptions of the other HDI08 configuration registers. Freescale Semiconductor Input Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the DSP clock ...

Page 16

... Port B 9—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input tolerant. DSP56362 Technical Data, Rev. 4 Signal Description Freescale Semiconductor ...

Page 17

... HWR/HWR Input PB12 Input, Output, or Disconnected Freescale Semiconductor Table 2-9 Host Interface (continued) State during Reset GPIO Disconnected Host Address Input 2—When the HDI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus. ...

Page 18

... Port B 13—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input tolerant. DSP56362 Technical Data, Rev. 4 Signal Description Freescale Semiconductor ...

Page 19

... HRRQ/HRRQ Output PB15 Input, Output, or Disconnected Freescale Semiconductor Table 2-9 Host Interface (continued) State during Reset GPIO Disconnected Host Request—When HDI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host request (HOREQ) output. The polarity of the host request is programmable, but is configured as active-low (HOREQ) following reset ...

Page 20

... Thus, there is no need for an external pull-up in this state. This input tolerant. DSP56362 Technical Data, Rev. 4 Signal Description 2 C bus transactions in the through a pull-up resistor mode, SDA is a Schmitt-trigger through a pull-up resistor. SDA transactions. The data in SDA must be stable Freescale Semiconductor 2 C mode. ...

Page 21

... Input SS Input HA2 Input HREQ Input or Output Freescale Semiconductor State during Reset Tri-Stated SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data ...

Page 22

... IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. Port C 1—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input tolerant. DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 23

... SDI0 Input PC6 Input, Output, or Disconnected Freescale Semiconductor Signal Description input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port C 4— ...

Page 24

... The default state after reset is GPIO disconnected. This input tolerant. serial transmit shift register. Port C 11—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input tolerant. DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 25

... Type State During Reset Name TIO0 Input or Output Freescale Semiconductor Disconnected Audio Clock Input—This is the DAX clock input. When programmed to use an external clock, this input supplies the DAX clock. The external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 × ...

Page 26

... All other interface with the OnCE module must occur through the JTAG port. The use not recommended for new designs recommended to leave DE disconnected. This input is not 5 V tolerant. DSP56362 Technical Data, Rev. 4 Signal Description Freescale Semiconductor ...

Page 27

... Rating Supply Voltage All input voltages excluding “5 V tolerant” inputs 3 All “5 V tolerant” input voltages Current drain per pin excluding V and GND CC Freescale Semiconductor CAUTION ). The suggested value for a pullup or pulldown CC NOTE Table 3-1 Maximum Ratings Symbol ...

Page 28

... LQFP Value 45.3 JA 10.1 JC 5.5 1 Min Typ Max 3.14 3.3 3.46 2.0 — 2.0 — 3. 3.95 1.5 CC — –0.3 — 0.8 –0.3 — 0.8 0.3 × V –0.3 — 0.2 × V –0.3 Freescale Semiconductor Unit °C °C Unit °C/W °C/W °C/W Unit ...

Page 29

... DSP56362 output levels are measured with the production test machine V at 0.4 V and 2.4 V, respectively. Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed. Freescale Semiconductor Symbol Min I –10 ...

Page 30

... ET — C 0.51 × ET × PDF × — C DF/MF 0.53 × ET × PDF × — C DF/MF ET — C 0.51 × ET × PDF × — C DF/MF 0.53 × ET × PDF × — C DF/MF × PDF × DF/MF ET — × ET — — C Freescale Semiconductor ...

Page 31

... EXTAL input low • With PLL disabled (46.7%–53.3% duty cycle) • With PLL enabled (42.5%–57.5% duty cycle EXTAL cycle time • With PLL disabled • With PLL enabled 5 CLKOUT change from EXTAL fall with PLL disabled Freescale Semiconductor ETL ETC ...

Page 32

... MHz 120 MHz Min Max Min 0.0 ns 1.8 ns 0.0 ns 1.8 ns 0.0 ns 1.8 ns ∞ 0.00 ns 8.53 µs 8.53 µs 0.00 ns 100 MHz Unit Max 200 MHz (MF × 780) − 140 MF × 1470 ). The recommended value in pF for CCP Freescale Semiconductor Max pF pF ...

Page 33

... Caused by first interrupt instruction fetch • Caused by first interrupt instruction execution 18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing 2 Expression 3 — ...

Page 34

... Note 7 — Note 7 4.9 5.9 93.5 — 78.1 — 252.5 — 211.2 5.9 — 4.9 1.3 13.6 — C 232.5 ns 12.3 ms — C 77.5 87.5 64.6 72.9 C 13.6 — C 12.3 — C 55.0 — 45.8 Freescale Semiconductor Unit — ns — — ns — ms — — ns ...

Page 35

... The maximum value for ET is 4096 (maximum MF) divided by the desired internal frequency C (i.e., for 100 MHz it is 4096/100 MHz = 40.96µs). During the stabilization period, T width may vary, so timing may vary as well. Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing 2 Expression 12T ...

Page 36

... Reset, Stop, Mode Select, and Interrupt Timing RESET 8 All Pins A0–A17 CLKOUT 11 RESET A0–A17 3-10 9 Reset Value Figure 3-2 Reset Timing 12 Figure 3-3 Synchronous Reset Timing DSP56362 Technical Data, Rev First Fetch AA0460 AA0461 Freescale Semiconductor ...

Page 37

... IRQA, IRQB, IRQC, IRQD, NMI IRQA, IRQB, IRQC, IRQD, NMI IRQA, IRQB, IRQC, IRQD, NMI Figure 3-5 External Interrupt Timing (Negative Edge-Triggered) Freescale Semiconductor First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General Purpose I/O Figure 3-4 External Fast Interrupt Timing ...

Page 38

... RESET MODA, MODB, MODC, MODD, PINIT IRQA A0–A17 Figure 3-8 Recovery from Stop State Using IRQA 3- Figure 3-7 Operating Mode Select Timing 24 25 DSP56362 Technical Data, Rev AA0464 IRQA, IRQB IRQC, IRQD, NMI V IL AA0465 First Instruction Fetch AA0466 Freescale Semiconductor ...

Page 39

... Figure 3-9 Recovery from Stop State Using IRQA Interrupt Service A0–A17 RD WR IRQA, IRQB, IRQC, IRQD, NMI Figure 3-10 External Memory Access (DMA Source) Timing Freescale Semiconductor 26 25 DMA Source Address 29 First Interrupt Instruction Execution DSP56362 Technical Data, Rev. 4 Reset, Stop, Mode Select, and Interrupt Timing ...

Page 40

... Freescale Semiconductor Unit ...

Page 41

... RD deassertion to data not valid (data hold time) 107 Address valid to WR deassertion 108 Data valid to WR deassertion (data setup time) 109 Data hold time from WR deassertion 4 110 WR assertion to data active 111 WR deassertion to data high impedance Freescale Semiconductor Symbol Expression 100 MHz (WS + 0.75) × T [WS ≥ ...

Page 42

... Freescale Semiconductor Unit ...

Page 43

... Timings 100, 107 are guaranteed by design, not tested. 4 Timing 110, 111, and 112, are not specified for 100 MHz the case of TA negation: timing 118 is relative to the deassertion edge were TA to remain active. A0–A17 AA0–AA3 D0–D23 Freescale Semiconductor Symbol Expression 5 0.25 × 100 113 116 115 105 ...

Page 44

... Figure 3-12 SRAM Write Access Figure 3-13 and Figure 3-16 should be used for primary selection only. DSP56362 Technical Data, Rev. 4 103 118 111 109 Data Out AA0469 Freescale Semiconductor ...

Page 45

... CAS deassertion to data not valid (read hold time) 135 Last CAS assertion to RAS deassertion 136 Previous CAS deassertion to RAS deassertion Freescale Semiconductor Note: This figure should be used for primary selection. For exact and detailed timings see the following tables. 120 ...

Page 46

... C equals 2 × Figure 3-13 . and not t . OFF GZ Freescale Semiconductor Unit for C ...

Page 47

... Last WR assertion to RAS deassertion 148 WR assertion to CAS deassertion 149 Data valid to CAS assertion (write) 150 CAS assertion to data not valid (write) 151 WR assertion to CAS assertion 152 Last RD assertion to RAS deassertion Freescale Semiconductor External Memory Expansion Port (Port A) Symbol CAC OFF ...

Page 48

... C 4.5 × T − 4.0 41.0 — × T − 4.0 16.0 — 2.25 × T − 6.0 — — C 3.75 × T − 6.0 — — C 4.75 × T − 6.0 41.5 — C 6.75 × T − 6.0 61.5 — C Freescale Semiconductor for ...

Page 49

... All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t read-after-read or write-after-write sequences). 5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access deassertion will always occur after CAS deassertion; therefore, the restricted timing is t Freescale Semiconductor Symbol ASC t ...

Page 50

... C 8.5 — 6.4 — − 4.0 C − 4.2 28.3 — 22.9 — C − 4.5 40.5 — 33.0 — − 4.3 43.2 — 35.3 — C − 4.3 33.2 — 26.9 — C Freescale Semiconductor Unit ...

Page 51

... All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t read-after-read or write-after-write sequences). 5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access deassertion will always occur after CAS deassertion; therefore, the restricted timing is t Freescale Semiconductor Symbol Expression 0.5 × 3.5 × T ...

Page 52

... Column Column Address Address 151 144 145 146 155 150 149 Data Out Data Out DSP56362 Technical Data, Rev. 4 136 135 138 142 Last Column Address 143 147 148 156 Data Out AA0473 Freescale Semiconductor ...

Page 53

... RAS CAS Row A0–A17 Add WR RD D0–D23 Figure 3-15 DRAM Page Mode Read Accesses Freescale Semiconductor 131 137 139 140 141 Column Column Address Address 143 133 153 Data In Data In DSP56362 Technical Data, Rev. 4 External Memory Expansion Port (Port A) 136 135 ...

Page 54

... Freescale Semiconductor 4 Unit — — ns — ns — ns — ns ...

Page 55

... Data valid to CAS assertion (write) 186 CAS assertion to data not valid (write) 187 RAS assertion to data not valid (write) 188 WR assertion to CAS assertion 189 CAS assertion to RAS assertion (refresh) 190 RAS deassertion to CAS assertion (refresh) Freescale Semiconductor 3 Symbol Expression 2.75 × CSH C 1.25 × CAS C 1.5 × ...

Page 56

... T − 4.0 24.1 — C 2.5 × T ± 2 29.3 33.3 C 1.75 × T ± 2 19.9 23.9 C 4.25 × T − 4.0 49.1 — C 2.75 × T − 4.0 30.4 — C 3.25 × T − 4.0 36.6 — C Freescale Semiconductor 4 Unit — — ns — ns 8.3 ns Unit ...

Page 57

... The refresh period is specified in the DCR deassertion will always occur after CAS deassertion; therefore, the restricted timing The asynchronous delays specified in the expressions are valid for DSP56362. 5 Either must be satisfied for read cycles. RCH RRH Freescale Semiconductor 3 Symbol t RAH t ASC t CAH t AR ...

Page 58

... C − 4.0 73.5 — × T − 4.0 56.0 — 3.0 × T − 4.0 26.0 — − 4.0 13.5 — − 3.0 — — − 2.0 0.5 — × T − 4.2 45.8 — 7.5 × T − 4.2 70.8 — Freescale Semiconductor ...

Page 59

... Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz No. Characteristics 157 Random read or write cycle time 158 RAS assertion to data valid (read) 159 CAS assertion to data valid (read) 160 Column address valid to data valid (read) Freescale Semiconductor 3 Symbol RWL t CWL t DS ...

Page 60

... Freescale Semiconductor Unit ...

Page 61

... The number of wait states for out-of-page access is specified in the DCR. 2 The refresh period is specified in the DCR deassertion will always occur after CAS deassertion; therefore, the restricted timing Either must be satisfied for read cycles. RCH RRH Freescale Semiconductor 3 Symbol Expression 6.25 × 9.75 × DHR C 9.5 × ...

Page 62

... Figure 3-17 DRAM Out-of-Page Read Access 3-36 157 163 165 167 164 168 170 166 171 173 175 Row Address Column Address 172 176 177 191 160 159 158 192 DSP56362 Technical Data, Rev. 4 162 174 179 168 193 161 Data In AA0476 Freescale Semiconductor ...

Page 63

... RAS 169 CAS A0–A17 WR RD D0–D23 Figure 3-18 DRAM Out-of-Page Write Access Freescale Semiconductor 157 163 165 167 164 168 170 166 171 173 172 176 Row Address Column Address 181 175 188 180 182 184 183 187 186 185 ...

Page 64

... T + 4.0 — 6.5 C 0.25 × T 2.5 — C 4.0 — 0.0 — 0.25 × T 2.5 — C 0.25 × 4.0 3.3 6.5 C 0.25 × T 2.5 — C 0.25 × T — 2.5 C 4.0 — 0.0 — 0.75 × 4.0 8.2 11.5 C Freescale Semiconductor Unit ...

Page 65

... T198 and T199 are valid for Address Trace mode if the ATE bit in the OMR is set. Use the status of BR (See T212) to determine whether the access referenced by A0–A23 is internal or external, when this mode is enabled > assertion refers to the next rising edge of CLKOUT. Freescale Semiconductor 5 DSP56362 Technical Data, Rev. 4 External Memory Expansion Port (Port A) ...

Page 66

... A0–A17 AA0–AA3 TA WR D0–D23 RD D0–D23 Figure 3-20 Synchronous Bus Timings SRAM 1 WS (BCR Controlled) 3-40 198 210 203 Data Out 202 208 206 DSP56362 Technical Data, Rev. 4 199 201 200 211 205 204 209 207 Data In AA0479 Freescale Semiconductor ...

Page 67

... BG asserted/deasserted to CLKOUT high (setup) 214 CLKOUT high to BG deasserted/asserted (hold) 215 BB deassertion to CLKOUT high (input setup) 216 CLKOUT high to BB assertion (input hold) 217 CLKOUT high to BB assertion (output) Freescale Semiconductor 201 200 203 Data Out 202 206 Table 3-18 Arbitration Bus Timings 2 DSP56362 Technical Data, Rev ...

Page 68

... DSP56362 Technical Data, Rev. 4 (continued) 100 MHz Expression Min Max 1.0 4.0 — 4.5 0.25 × T 2.5 — C 0.25 × T — 2.5 C 0.25 × T 2.5 — C 0.25 × 4.0 3.2 6.5 C 0.75 × T — 7.5 C 217 222 AA0481 Freescale Semiconductor Unit ...

Page 69

... CLKOUT 212 A0–A17 RD, WR AA0–AA3 Figure 3-23 Bus Release Timings Case 1 (BRT Bit in OMR Cleared) Freescale Semiconductor External Memory Expansion Port (Port A) 214 213 219 218 221 224 223 DSP56362 Technical Data, Rev. 4 AA0482 3-43 ...

Page 70

... In order to guarantee timings 250, and 251 recommended to assert BG inputs to different 56300 devices (on the same bus non overlap manner as shown in 3-44 214 213 221 224 223 Expression 2 . Table 3-19 Figure 3-25 . DSP56362 Technical Data, Rev. 4 219 218 AA0483 100 MHz Unit Min Max — — required. Freescale Semiconductor ...

Page 71

... BG asserted, and BB negated, may cause another 56300 component to assume mastership at the same time. Therefore some non-overlap period between one BG input active to another BG input active, is required. Timing 251 ensures that such a situation is avoided. Freescale Semiconductor External Memory Expansion Port (Port A) 250 250+251 DSP56362 Technical Data, Rev ...

Page 72

... C 16.5 — — 9.9 — — 0.0 — — 9.9 — — 3.3 — — 3.3 — — — 24.2 — — 9.9 — 3.3 — T +9.9 19.9 — C — 9.9 — — — 19.1 Freescale Semiconductor Unit ...

Page 73

... This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal. 7 This timing is applicable only if two consecutive reads from one of these registers are executed. Freescale Semiconductor 3 Expression 9 ...

Page 74

... HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-28 Read Timing Diagram, Non-Multiplexed Bus 3-48 317 327 329 326 336 337 333 330 317 318 328 332 319 327 329 326 340 341 DSP56362 Technical Data, Rev. 4 318 328 AA1105 338 AA0484 Freescale Semiconductor ...

Page 75

... HA0–HA2 HCS HWR, HDS HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-29 Write Timing Diagram, Non-Multiplexed Bus Freescale Semiconductor 336 331 320 321 324 340 341 DSP56362 Technical Data, Rev. 4 Parallel Host Interface (HDI08) Timing 337 333 325 339 AA0485 3-49 ...

Page 76

... HAS HRD, HDS HAD0–HAD7 HOREQ, HRRQ, HTRQ Figure 3-30 Read Timing Diagram, Multiplexed Bus 3-50 336 337 323 317 334 335 327 328 329 Address Data 326 340 341 DSP56362 Technical Data, Rev. 4 318 319 338 AA0486 Freescale Semiconductor ...

Page 77

... HAS HWR, HDS HAD0–HAD7 HOREQ, HRRQ, HTRQ Figure 3-31 Write Timing Diagram, Multiplexed Bus HOREQ (Output) HACK (Input) H0–H7 (Input) Figure 3-32 Host DMA Write Timing Diagram Freescale Semiconductor 336 323 320 334 324 335 Data Address 340 341 342 ...

Page 78

... C 2.5×T +189 214 — C 0.5×t –10 43 — SPICC 0.5×t –10 96 — SPICC 0.5×t –10 131 — SPICC 2.5×T +12 37 — C 2.5×T +102 127 — C 2.5×T +189 214 — C Freescale Semiconductor Unit ...

Page 79

... SS assertion to data out valid (CPHA = 0) 157 First SCK sampling edge to HREQ output deassertion 158 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Freescale Semiconductor Serial Host Interface SPI Protocol Timing Mode Filter Mode Master — Slave — Slave ...

Page 80

... — C 0.5 × 121 — SPICC 2.5×T +43 C 0.5 ×t + 174 — SPICC 2.5×T +43 C 0.5 ×t + 209 — SPICC 2.5×T + — — 141 144 141 144 149 LSB Valid 153 LSB AA0271 Freescale Semiconductor Unit ...

Page 81

... SS (Input) SCK (CPOL = 0 (Output) SCK (CPOL = 1 (Output) MISO (Input) MOSI (Output) 161 HREQ (Input) Freescale Semiconductor 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 162 163 Figure 3-35 SPI Slave Timing (CPHA = 0) DSP56362 Technical Data, Rev. 4 Serial Host Interface SPI Protocol Timing ...

Page 82

... HREQ (Input) 3-56 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 162 163 Figure 3-36 SPI Master Timing (CPHA = 1) DSP56362 Technical Data, Rev. 4 141 144 141 144 148 149 LSB Valid 153 LSB AA0272 Freescale Semiconductor ...

Page 83

... SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 154 150 MISO (Output) 148 MOSI (Input) HREQ (Output) Freescale Semiconductor 143 144 142 144 143 152 153 153 MSB 148 149 MSB Valid 157 Figure 3-37 SPI Slave Timing (CPHA = 0) DSP56362 Technical Data, Rev. 4 ...

Page 84

... HREQ (Output) 3-58 143 144 142 144 143 152 MSB 148 149 MSB Valid 157 Figure 3-38 SPI Slave Timing (CPHA = 1) DSP56362 Technical Data, Rev. 4 141 147 144 144 153 151 LSB 148 149 LSB Valid 158 AA0274 Freescale Semiconductor ...

Page 85

... HREQ in deassertion to last SCL edge (HREQ in set-up time) 186 First SCL sampling edge to HREQ output deassertion Filters bypassed Narrow filters enabled Wide filters enabled Freescale Semiconductor Serial Host Interface (SHI Protocol Timing 2 Table 3-22 SHI I C Protocol Timing 2 Standard I C* ...

Page 86

... Table 3-23 DSP56362 Technical Data, Rev. 4 Standard Fast-Mode Max Min Max — 50 — — 100 — — 155 — — 927 — — 882 — — 838 — × HRS ) ) ] 7 – and the filters selected should be chosen Freescale Semiconductor Unit ns ns ...

Page 87

... CCP Choosing HRS = 0 gives HDM Thus the HDM[7:0] value should be programmed to $38 (=56). 173 176 SCL 177 172 SDA Stop Start 174 188 HREQ Freescale Semiconductor 2 + 2.5 × CCP 2 + 2.5 × CCP + 2.5 × CCP = 10ns), operating in a standard-mode 1000ns), with filters bypassed R × ...

Page 88

... C 454 10.0 — 15.0 — 10.0 — 15.0 — — 37 — 22 — 37 — 22 — 39 — — 24 — 36 — 21 — 37 — 22 0.0 — 19.0 — 5.0 — 3.0 — 23.0 — 1.0 — 1.0 — 23.0 — Freescale Semiconductor 4 Unit ...

Page 89

... TXC rising edge to data out valid 455 TXC rising edge to data out high impedance 456 TXC rising edge to transmitter drive enable 7 deassertion 457 FST input (bl, wr) setup time before TXC falling 6 edge Freescale Semiconductor 2, 3 Symbol Expression — — — — ...

Page 90

... L DSP56362 Technical Data, Rev. 4 100 MHz 4 Condition Unit Min Max — 27.0 — ns — 31.0 — ns 2.0 — 21.0 — 4.0 — 0.0 — — 32 — 18 40.0 — ns — 27.5 ns — 27.5 ns Freescale Semiconductor ...

Page 91

... FST (Bit) In FST (Word) In Flags Out Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. Freescale Semiconductor 430 432 446 447 450 ...

Page 92

... HCKT SCKT(output) 3-66 430 431 432 433 434 437 439 First Bit 441 443 442 444 Figure 3-41 ESAI Receiver Timing 463 464 Figure 3-42 ESAI HCKT Timing DSP56362 Technical Data, Rev. 4 438 440 Last Bit 443 445 AA0491 Freescale Semiconductor ...

Page 93

... In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56362 internal clock frequency. For example, if the DSP56362 is running at 100 MHz internally, the ACI frequency should be less than 50 MHz. ACI 223 ADO Figure 3-44 Digital Audio Transmitter Timing Freescale Semiconductor 463 465 Figure 3-43 ESAI HCKR Timing Expression — 2 × 0.5 × ...

Page 94

... Max 2 × 2.0 22.0 — × 2.0 22.0 — C 9.0 10.0 10.25 × 1.0 103.5 — C 0.5 × 3.5 8.5 — C 0.5 × 19.8 — 24.8 C 0.5 × 3.5 8.5 — C 0.5 × 19.0 — 24.8 C AA0492 AA0493 Freescale Semiconductor Unit ...

Page 95

... Fetch to CLKOUT edge before GPIO change 495 GPIO out rise time 496 GPIO out fall time 3.3 V ± 0. 0°C to +100° Freescale Semiconductor 484 Figure 3-47 External Pulse Generation Table 3-27 GPIO Timing Expression 6.75 × DSP56362 Technical Data, Rev. 4 GPIO Timing 485 ...

Page 96

... Figure 3-48 GPIO Timing Table 3-28 JTAG Timing Characteristics × 3); maximum 22 MHz) C DSP56362 Technical Data, Rev. 4 490 491 AA0495 1, 2 All Frequencies Min Max 0.0 22.0 45.0 — 20.0 — 0.0 3.0 5.0 — 24.0 — 0.0 40.0 0.0 40.0 Freescale Semiconductor Unit MHz ...

Page 97

... V ± 0.16V 0°C to +100° All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. V TCK (Input) 503 Figure 3-49 Test Clock Input Timing Diagram Freescale Semiconductor 1, 2 Table 3-28 JTAG Timing (continued) Characteristics = 501 502 V M ...

Page 98

... Figure 3-51 Test Access Port Timing Diagram 3-72 504 Input Data Valid 506 Output Data Valid 507 506 Output Data Valid 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid DSP56362 Technical Data, Rev. 4 VIH 505 AA0497 VIH 509 AA0498 Freescale Semiconductor ...

Page 99

... Response time when DSP56362 is executing NOP instructions from internal memory 516 Debug acknowledge assertion time 3.3 V ± 0. 0°C to +100° 514 Freescale Semiconductor 513 Figure 3-52 TRST Timing Diagram Table 3-29 OnCE Module Timing Expression 1/(T max 22.0 MHz 1.5 × T 5.5 × × 515 Figure 3-53 OnCE— ...

Page 100

... OnCE Module TimIng 3-74 NOTES DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 101

... Descriptions” are allocated for the package. The DSP56362 is available in a 144-pin LQFP package. 4.2 LQFP Package Description Top view of the LQFP package is shown in drawing is shown in Figure 4-2. Freescale Semiconductor Section 2, “Signal/Connection Figure 4-1 with its pin-outs. The LQFP package mechanical DSP56362 Technical Data, Rev. 4 4-1 ...

Page 102

... DSP56362 Technical Data, Rev AA0 AA1 RD WR GND C V CCC PINIT nc CLKOUT GND C V CCC V CCQL EXTAL GND Q DE CAS AA2 AA3 V CCQH GND P1 GND P PCAP V CCP RESET HAD0 HAD1 HAD2 HAD3 GND H V CCH HAD4 37 Table 4-1 AA0301 Freescale Semiconductor ...

Page 103

... CCQL 19 GND CCQH 21 HDS/HDS, HWR/HWR, or PB12 22 HRW, HRD/HRD, or PB11 23 HACK/HACK, HRRQ/HRRQ, or PB15 24 HOREQ/HOREQ, HTRQ/HTRQ, or PB14 25 V CCS Freescale Semiconductor 1 Pin No. Signal Name 26 GND S 27 ADO or PD1 28 ACI or PD0 29 TIO0 30 HCS/HCS, HA10, or PB13 31 HA2, HA9, or PB10 32 HA1, HA8, or PB9 33 HA0, HAS/HAS, or PB8 ...

Page 104

... D19 126 V CCQL 127 GND Q 128 D20 129 V CCD 130 GND D 131 D21 132 D22 133 D23 134 MODD/IRQD 135 MODC/IRQC 136 MODB/IRQB 137 MODA/IRQA 138 TRST 139 TDO 140 TDI 141 TCK 142 TMS 143 MOSI/HA0 144 MISO/SDA Freescale Semiconductor ...

Page 105

... A16 98 A17 AA0 70 AA1 69 AA2 51 AA3 50 ACI 28 ADO Freescale Semiconductor Signal Name Pin No. D13 117 D14 118 D15 121 D16 122 D17 123 D18 124 D19 125 D2 102 D20 128 D21 131 D22 132 D23 133 D3 105 D4 106 D5 107 D6 108 D7 109 ...

Page 106

... Pin No. HAD3 40 HAD4 37 HAD5 36 HAD6 35 HAD7 34 HAS/HAS 33 HCS/HCS 30 HDS/HDS 21 SDO3 7 SDO4 10 SDO5 TCK 141 TDI 140 TDO 139 TIO0 29 TMS 142 TRST 138 V 74 CCA V 80 CCA V 86 CCA V 57 CCC V 65 CCC V 103 CCD V 111 CCD V 119 CCD Freescale Semiconductor ...

Page 107

... Table 4-2 DSP56362 LQFP Signal Identification by Name (continued) Signal Name Pin No. NMI 61 PB0 43 PB1 42 PB10 31 PB11 22 PB12 21 PB13 30 PB14 24 PB15 23 PB2 41 PB3 40 PB4 37 PB5 36 PB6 35 PB7 34 PB8 33 Freescale Semiconductor Signal Name Pin No. RAS2 52 RAS3 RESET 44 SCK 1 SCKR 15 SCKT 14 SCL 1 SDA 144 SDI0 11 SDI1 10 SDI2 7 SDI3 6 SDO0 4 SDO1 5 SDO2 6 DSP56362 Technical Data, Rev ...

Page 108

... LQFP Package Mechanical Drawing 4.3 LQFP PACKAGE MECHANICAL DRAWING Figure 4-2 DSP56362 144-pin LQFP Package 4-8 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 109

... Again, if the estimations obtained from R the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages. Freescale Semiconductor , in °C can be obtained from the following equation × ...

Page 110

... IRQB, IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order inches) are recommended. 5 determined by a thermocouple, the thermal resistance T CAUTION ). The suggested value for a pullup or pulldown resistor CC power source to GND. CC DSP56362 Technical Data, Rev has been defined JT pin on the DSP and from CC and GND. CC Freescale Semiconductor and CC ...

Page 111

... Minimize external memory accesses and use internal memory accesses. • Minimize the number of pins that are switching. • Minimize the capacitive load on the pins. • Connect the unused inputs to pull-up or pull-down resistors. Freescale Semiconductor and GND circuits GND CCP × × ...

Page 112

... MHz and MF ≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than ±2 ns. 5 1MHz = – I typF2 typF1 NOTE DSP56362 Technical Data, Rev. 4 × – Freescale Semiconductor ...

Page 113

... Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive instead of 11. If the combination of HF3 and HF2 has Freescale Semiconductor DSP56362 Technical Data, Rev. 4 Host Port Considerations ...

Page 114

... HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small probability exists that the DSP will read the status bits synchronized during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus. 5-6 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 115

... Ordering Information Consult a Freescale Semiconductor, Inc. sales office or authorized distributor to determine product availability and to place an order. For information on ordering this and all DSP Audio products, review the SG1004 selector guide at http://www.freescale.com. Freescale Semiconductor DSP56362 Technical Data, Rev. 4 6-1 ...

Page 116

... NOTES DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 117

... PLOAD_LOOP ; ; Load the X-data ; move move Freescale Semiconductor 200,55,0,0,0 ; Interrupt vectors for program debug only ; MAIN (external) program starting address ; INTERNAL X-data memory starting address ; INTERNAL Y-data memory starting address P:START #$0d0000,x:M_PCTL ; PLL enable ; CLKOUT disable #INT_PROG,r0 ...

Page 118

... INT_PROG #$0,r0 #$0,r4 #$3f,m0 #$3f, #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr ; ebd #60,_end x0,y0,a x:(r0)+,x1 x1,y1,a x:(r0)+,x0 a,b x0,y0,a x:(r0)+,x1 x1,y1,a b1,x:$ff sbr x:0 $262EB9 $86F2FE $E56A5F $616CAC DSP56362 Technical Data, Rev. 4 y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 Freescale Semiconductor ...

Page 119

... Freescale Semiconductor $8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 $6C6657 $C2A544 $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 $A57347 $4BE774 $8F349D $A1ED12 $4BFCE3 $EA26E0 $CD7D99 $4BA85E $27A43F $A8B10C $D3A55 $25EC6A $2A255B $A5F1F8 $2426D1 $AE6536 $CBBC37 ...

Page 120

... DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 121

... YDAT_END Freescale Semiconductor $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245 DSP56362 Technical Data, Rev. 4 A-5 ...

Page 122

... A-6 NOTES DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 123

... Freescale Semiconductor 2.1 min 45m 22m 2.5nH 1.1nH 1.3pF 1.2pF ip5b_io ip5b_io ip5b_io ip5b_io ip5b_io ip5b_io ip5b_io power gnd ip5b_io ip5b_io ...

Page 124

... DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 125

... Freescale Semiconductor icba_o gnd power icba_o icba_o icba_o power gnd icba_o icba_o icba_o icba_io icba_io ...

Page 126

... I/O 5.00pF 5.00pF 3.3v 3v 3.6v I(min) I(max) -3.65e+02 -5.18e+02 -3.30e+02 -4.67e+02 -2.94e+02 -4.16e+02 -2.59e+02 -3.65e+02 -2.23e+02 -3.14e+02 -1.88e+02 -2.63e+02 -1.52e+02 -2.12e+02 -1.17e+02 -1.61e+02 -9.25e+01 -1.10e+02 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 127

... I(typ) | -3.30e+00 2.922e-04 -3.10e+00 2.881e-04 -2.90e+00 2.853e-04 -2.70e+00 2.836e-04 -2.50e+00 2.825e-04 -2.30e+00 2.819e-04 -2.10e+00 2.815e-04 -1.90e+00 2.813e-04 -1.70e+00 2.812e-04 Freescale Semiconductor -6.88e+01 -7.58e+01 -4.52e+01 -4.17e+01 -2.15e+01 -7.69e+00 -1.18e+00 -5.63e-02 -2.25e-02 -4.28e-02 -1.38e-02 -3.12e-02 -8.35e-03 -1.91e-02 -2.80e-03 -6.52e-03 2.744e-03 6.427e-03 7.871e-03 1.823e-02 1 ...

Page 128

... I(min) I(max) -3.65e+02 -5.18e+02 -3.30e+02 -4.67e+02 -2.94e+02 -4.16e+02 -2.59e+02 -3.65e+02 -2.23e+02 -3.14e+02 -1.88e+02 -2.63e+02 -1.52e+02 -2.12e+02 -1.17e+02 -1.61e+02 -9.25e+01 -1.10e+02 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 129

... Freescale Semiconductor -6.88e+01 -7.58e+01 -4.52e+01 -4.17e+01 -2.15e+01 -7.67e+00 -1.18e+00 -7.81e-03 -5.70e-03 -8.42e-04 -4.53e-05 -1.00e-05 -3.74e-07 -8.58e-09 -3.00e-09 -3.64e-11 -5.14e-10 -2.79e-11 I(min) I(max) 0 ...

Page 130

... DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 131

... R_load = 50.00 |voltage I(typ Freescale Semiconductor -1.88e-02 -4.55e-02 -1.95e-02 -4.85e-02 -2.00e-02 -5.09e-02 -2.04e-02 -5.27e-02 -2.07e-02 -5.41e-02 -2.10e-02 -5.51e-02 -2.12e-02 -5.60e-02 -2.15e-02 -5.67e-02 -2.17e-02 -5.74e-02 -2.18e-02 -5.79e-02 -2 ...

Page 132

... DSP56362 Technical Data, Rev. 4 1.320/0.366 1.520/0.431 Freescale Semiconductor ...

Page 133

... Freescale Semiconductor 1.451e+01 2.015e-01 2.658e+01 2.030e-01 3.866e+01 2.385e-01 5.076e+01 9.563e+00 6.461e+01 2.682e+01 8.261e+01 4.409e+01 1.006e+02 6.258e+01 1.186e+02 8.836e+01 1.366e+02 1.141e+02 1.546e+02 1 ...

Page 134

... I(min) I(max) 1.905e+02 2.686e+02 1.725e+02 2.428e+02 1.545e+02 2.170e+02 1.365e+02 1.912e+02 1.185e+02 1.655e+02 1.005e+02 1.397e+02 8.253e+01 1.139e+02 6.454e+01 8.814e+01 5.068e+01 6.237e+01 3.859e+01 4.389e+01 2.651e+01 2.662e+01 1.444e+01 9.359e+00 2.517e+00 3.554e-02 1.577e-02 9.211e-04 7.857e-05 1.655e-05 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 135

... Freescale Semiconductor 6.836e-07 1.946e-08 7.379e-09 7.622e-11 2.438e-09 6.240e-11 I(min) I(max) 1.360/0.329 1.310/0.442 3-state 5.00pF 5.00pF 3.3v 3v 3.6v I(min) I(max) -3.65e+02 -5.18e+02 -3 ...

Page 136

... DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 137

... I(typ) | -3.30e+00 2.686e+02 -3.10e+00 2.428e+02 -2.90e+00 2.170e+02 -2.70e+00 1.912e+02 -2.50e+00 1.655e+02 -2.30e+00 1.397e+02 -2.10e+00 1.139e+02 -1.90e+00 8.814e+01 Freescale Semiconductor -7.85e-02 -2.10e-01 -7.93e-02 -2.13e-01 -8.00e-02 -2.15e-01 -8.06e-02 -2.17e-01 -8.13e-02 -2.19e-01 -8.84e-02 -2.21e-01 -1.26e+00 -2.22e-01 -2.16e+01 -2.24e-01 -4.53e+01 -2.27e-01 -6.89e+01 -2.38e-01 -9 ...

Page 138

... DSP56362 Technical Data, Rev. 4 1.900/0.124 1.880/0.155 Freescale Semiconductor ...

Page 139

... Freescale Semiconductor 8.240e-03 2.162e-02 4.783e-02 2.331e-02 4.994e-02 1.302e-01 5.118e-02 1.369e-01 5.184e-02 1.412e-01 5.223e-02 1.436e-01 5.251e-02 1.449e-01 5.274e-02 1.458e-01 5.293e-02 1.464e-01 5.309e-02 1 ...

Page 140

... I(min) I(max) 1.896e+02 2.677e+02 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 141

... Freescale Semiconductor 1.716e+02 2.420e+02 1.537e+02 2.163e+02 1.358e+02 1.906e+02 1.179e+02 1.649e+02 9.996e+01 1.392e+02 8.205e+01 1.135e+02 6.413e+01 8.778e+01 5.035e+01 6.208e+01 3.834e+01 4.368e+01 2.633e+01 2 ...

Page 142

... I(min) I(max) -3.65e+02 -5.17e+02 -3.29e+02 -4.66e+02 -2.94e+02 -4.15e+02 -2.58e+02 -3.64e+02 -2.23e+02 -3.13e+02 -1.88e+02 -2.62e+02 -1.52e+02 -2.11e+02 -1.17e+02 -1.60e+02 -9.24e+01 -1.10e+02 -6.87e+01 -7.57e+01 -4.51e+01 -4.17e+01 -2.15e+01 -7.66e+00 -1.17e+00 -3.79e-02 -1.67e-02 -2.81e-02 -9.77e-03 -2.04e-02 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 143

... Freescale Semiconductor -5.89e-03 -1.24e-02 -1.98e-03 -4.20e-03 1.940e-03 4.177e-03 5.578e-03 1.216e-02 8.907e-03 1.965e-02 1.191e-02 2.663e-02 1.455e-02 3.305e-02 1.680e-02 3.887e-02 1.862e-02 4.404e-02 1.997e-02 4 ...

Page 144

... I(min) I(max) -3.65e+02 -5.17e+02 -3.29e+02 -4.66e+02 -2.94e+02 -4.15e+02 -2.58e+02 -3.64e+02 -2.23e+02 -3.13e+02 -1.88e+02 -2.62e+02 -1.52e+02 -2.11e+02 -1.17e+02 -1.60e+02 -9.24e+01 -1.10e+02 -6.87e+01 -7.57e+01 -4.51e+01 -4.16e+01 -2.15e+01 -7.64e+00 -1.16e+00 -4.87e-03 -4.39e-03 -3.03e-04 -2.55e-05 -2.73e-06 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 145

... C_comp 5.00pF | | [Voltage Range] [GND_clamp] |voltage I(typ) | -3.30e+00 -5.21e+02 -3.10e+00 -4.70e+02 -2.90e+00 -4.19e+02 -2.70e+00 -3.68e+02 -2.50e+00 -3.17e+02 -2.30e+00 -2.66e+02 Freescale Semiconductor -1.91e-07 -2.57e-09 -2.47e-09 -2.19e-11 -1.17e-09 -1.84e-11 I(min) I(max) 1.885e+02 2.667e+02 1.707e+02 2.411e+02 1.528e+02 2.155e+02 1.350e+02 1.898e+02 1.172e+02 1.642e+02 9.935e+01 1.386e+02 8 ...

Page 146

... DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 147

... D data memory expansion 4 DAX electrical characteristics 2 Debug support 3 design considerations Freescale Semiconductor electrical 3 PLL 4, 5 power consumption 3 thermal 1 Digital Audio Transmitter 4, 16 DRAM out of page read access 36 wait states selection guide 28 write access 37 out of page and refresh timings ...

Page 148

... Wait state 12 J Jitter 5 JTAG 20 JTAG Port 3 reset timing diagram 73 timing 70 maximum ratings 1 Memory Expansion Port 3 mode control 8 Mode select timing 7 multiplexed bus 2 multiplexed bus timings read 50 write 51 N non-multiplexed bus 2 non-multiplexed bus timings read 48 write 49 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 149

... RAM 3 R recovery from Stop state using IRQA 12, 13 RESET 9 Reset timing 7, 10 synchronous 10 ROM, bootstrap 3 Freescale Semiconductor S Serial Host Interface 4, 14 SHI signal groupings 1 signals 1 functional grouping 2 SRAM 40 Access 38 read access 17 ...

Page 150

... OnCE™ (On Chip Emulator) Timing 62 Serial Host Interface (SHI) SPI Protocol Tim- ing 52 Serial Host Interface (SHI) Timing 52 timing interrupt 7 mode select 7 Reset 7 Stop 7 TQFP 1 pin list by number 3 pin-out drawing (top Wait mode data RAM data RAM 3 Index-4 DSP56362 Technical Data, Rev. 4 Freescale Semiconductor ...

Page 151

... Freescale Semiconductor DSP56362 Technical Data, Rev. 4 Index-5 ...

Page 152

... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...

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