XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 21

• Manufacturer Part Number: XCB56362PV100
• Description: DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
• Manufacturer: Freescale Semiconductor

Specifications of XCB56362PV100

• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 33 KB
• Device Million Instructions Per Second: 100 MIPS

Freescale Semiconductor
Signal Name
HREQ
MOSI
HA0
HA2
SS
Input or Output
Input or Output
Signal Type
Input
Input
Input
Table 2-10 Serial Host Interface Signals (continued)
State during
Tri-Stated
Tri-Stated
Tri-Stated
Reset
DSP56362 Technical Data, Rev. 4
SPI Master-Out-Slave-In—When the SPI is configured as a master,
MOSI is the master data output line. The MOSI signal is used in
conjunction with the MISO signal for transmitting and receiving serial
data. MOSI is the slave data input line when the SPI is configured as
a slave. This signal is a Schmitt-trigger input when configured for the
SPI Slave mode.
I
configured for the I
HA0 signal is used to form the slave device address. HA0 is ignored
when configured for the I
This signal is tri-stated during hardware, software, and individual
reset. Thus, there is no need for an external pull-up in this state.
This input is 5 V tolerant.
SPI Slave Select—This signal is an active low Schmitt-trigger input
when configured for the SPI mode. When configured for the SPI Slave
mode, this signal is used to enable the SPI slave for transfer. When
configured for the SPI master mode, this signal should be kept
deasserted (pulled high). If it is asserted while configured as SPI
master, a bus error condition is flagged. If SS is deasserted, the SHI
ignores SCK clocks and keeps the MISO output signal in the
high-impedance state.
I
configured for the I
the HA2 signal is used to form the slave device address. HA2 is
ignored in the I
This signal is tri-stated during hardware, software, and individual
reset. Thus, there is no need for an external pull-up in this state.
This input is 5 V tolerant.
Host Request—This signal is an active low Schmitt-trigger input when
configured for the master mode but an active low output when
configured for the slave mode.
When configured for the slave mode, HREQ is asserted to indicate
that the SHI is ready for the next data word transfer and deasserted at
the first clock pulse of the new data word transfer. When configured for
the master mode, HREQ is an input. When asserted by the external
slave device, it will trigger the start of the data word transfer by the
master. After finishing the data word transfer, the master will await the
next assertion of HREQ to proceed to the next transfer.
This signal is tri-stated during hardware, software, personal reset, or
when the HREQ1–HREQ0 bits in the HCSR are cleared. There is no
need for external pull-up in this state.
This input is 5 V tolerant.
2
2
C Slave Address 0—This signal uses a Schmitt-trigger input when
C Slave Address 2—This signal uses a Schmitt-trigger input when
2
C master mode.
2
2
C mode. When configured for I
C mode. When configured for the I
Signal Description
2
C master mode.
Serial Host Interface
2
C slave mode, the
2
C Slave mode,
2-15