XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 20

• Manufacturer Part Number: XCB56362PV100
• Description: DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
• Manufacturer: Freescale Semiconductor

Specifications of XCB56362PV100

• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 33 KB
• Device Million Instructions Per Second: 100 MIPS

Serial Host Interface
2.8
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I
2-14
Signal Name
MISO
SCK
SDA
SCL
Serial Host Interface
Input or Open-Drain
Input or Output
Input or Output
Input or Output
Signal Type
Output
Table 2-10 Serial Host Interface Signals
State during
Tri-Stated
Tri-Stated
Reset
DSP56362 Technical Data, Rev. 4
SPI Serial Clock—The SCK signal is an output when the SPI is
configured as a master and a Schmitt-trigger input when the SPI is
configured as a slave. When the SPI is configured as a master, the
SCK signal is derived from the internal SHI clock generator. When the
SPI is configured as a slave, the SCK signal is an input, and the clock
signal from the external master synchronizes the data transfer. The
SCK signal is ignored by the SPI if it is defined as a slave and the slave
select (SS) signal is not asserted. In both the master and slave SPI
devices, data is shifted on one edge of the SCK signal and is sampled
on the opposite edge where data is stable. Edge polarity is determined
by the SPI transfer protocol.
I
I
and an open-drain output when configured as a master. SCL should
be connected to V
This signal is tri-stated during hardware, software, and individual
reset. Thus, there is no need for an external pull-up in this state.
This input is 5 V tolerant.
SPI Master-In-Slave-Out—When the SPI is configured as a master,
MISO is the master data input line. The MISO signal is used in
conjunction with the MOSI signal for transmitting and receiving serial
data. This signal is a Schmitt-trigger input when configured for the SPI
Master mode, an output when configured for the SPI Slave mode, and
tri-stated if configured for the SPI Slave mode when SS is deasserted.
An external pull-up resistor is not required for SPI operation.
I
input when receiving and an open-drain output when transmitting.
SDA should be connected to V
carries the data for I
during the high period of SCL. The data in SDA is only allowed to
change when SCL is low. When the bus is free, SDA is high. The SDA
line is only allowed to change during the time SCL is high in the case
of start and stop events. A high-to-low transition of the SDA line while
SCL is high is a unique situation, and is defined as the start event. A
low-to-high transition of SDA while SCL is high is a unique situation
defined as the stop event.
This signal is tri-stated during hardware, software, and individual
reset. Thus, there is no need for an external pull-up in this state.
This input is 5 V tolerant.
2
2
2
C Serial Clock—SCL carries the clock for I
C mode. SCL is a Schmitt-trigger input when configured as a slave
C Data and Acknowledge—In I
CC
2
C transactions. The data in SDA must be stable
through a pull-up resistor.
Signal Description
CC
2
through a pull-up resistor. SDA
C mode, SDA is a Schmitt-trigger
2
C bus transactions in the
Freescale Semiconductor
2
C mode.