XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 73

• Manufacturer Part Number: XCB56362PV100
• Description: DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
• Manufacturer: Freescale Semiconductor

Specifications of XCB56362PV100

• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 33 KB
• Device Million Instructions Per Second: 100 MIPS

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7
Freescale Semiconductor
No.
333
334
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See Host Port Usage Considerations in the DSP56362 User Design Manual.
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
V
The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.
The “last data register” is the register at address $7, which is the last location to be read or written in data transfers. This is
RXL/TXL in the little endian mode (HBE = 0), or RXH/TXH in the big endian mode (HBE = 1).
This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.
This timing is applicable only if two consecutive reads from one of these registers are executed.
CC
= 3.3 V ± 0.16 V; T
HCS hold time after data strobe deassertion
Address (AD7–AD0) setup time before HAS deassertion
(HMUX=1)
Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before
data strobe assertion
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after
data strobe deassertion
Delay from read data strobe deassertion to host request
assertion for “Last Data Register” read
Delay from write data strobe deassertion to host request
assertion for “Last Data Register” write
Delay from data strobe assertion to host request deassertion for
“Last Data Register” read or write (HROD = 0)
Delay from data strobe assertion to host request deassertion for
“Last Data Register” read or write (HROD = 1, open drain Host
Request)
Delay from DMA HACK deassertion to HOREQ assertion
Delay from DMA HACK assertion to HOREQ deassertion
Delay from DMA HACK assertion to HOREQ deassertion for
“Last Data Register” read or write
• Read
• Write
• For “Last Data Register” read
• For “Last Data Register” write
• For other cases
• HROD = 0
• HROD = 1, open drain Host Request
5, 9, 10, 11
5
J
= 0°C to +100°C, C
9
Table 3-20 Host Interface (HDI08) Timing
Characteristics
9
5
5
DSP56362 Technical Data, Rev. 4
4, 5, 10
5, 8, 10
L
5, 11
3
= 50 pF
9
5, 9, 10
1.5 × T
Expression
2 × T
1, 2
2 × T
C
T
—
—
—
—
—
—
—
—
—
C
C
(continued)
+ 19.1
+ 19.1
C
Parallel Host Interface (HDI08) Timing
Min
39.1
34.1
0.0
4.7
3.3
4.7
3.3
0.0
10
20
—
—
—
—
0
100 MHz
300.0
300.0
Max
19.1
20.2
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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