PEB20256E-V21 Infineon Technologies, PEB20256E-V21 Datasheet - Page 4

• Manufacturer Part Number: PEB20256E-V21
• Description: IC CONTROLLER INTERFACE 388-BGA
• Manufacturer: Infineon Technologies

Specifications of PEB20256E-V21

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, PPP, Serial, TMA
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 200mA
• Power (watts): 3W
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Circuits: -
• Other names: PEB20256E-V21; PEB20256E-V21IN

Revision History:
Previous Version:
Major changes to document since last version
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Data Sheet
Page
Description
Pin Diagram added 16-Port mode
Pin Diagram added 28-Port mode
Remote payload loop block diagram redrawn
Swap the bit positions of TBRTC and TBFTC In the CSPEC_BUFFER
register as their bit postitions were not correct in the preliminary data sheet.
Swap the postions of TBRTC with TBFTC in Table 8-7, as their column
positions were not correct in the preliminary data sheet
Fixed typo in CSPEC_IMASK register, replaced ROFD with RFOD
Fixed typo in IQMASK, replaced ROFD with RFOD
Update voltage min/max information for
Ratings
Update timing Information for
Interface Pins)
Update timing Information for
Update timing Information for
Characteristics
Update timing Information for
Intel Bus Interface Timing Diagram modified. The setup and hold times for
“LD to LRDY” was not a valid timing parameter. Instead, the setup and hold
parameters for “LD to LRD” were specified.
Update timing Information for
(Master Mode)
Timing parameter (setup time) 67a was changed from “LD to LDRY” to ”LD
to LRD”, because it was not a valid timing parameter.
Timing parameter (hold time) 67b was changed from “LD to LDRY” to ”LD
to LRD”, because it was not a valid timing parameter.
Update timing Information for
Update timing Information for
(Master Mode)
04.2001
Preliminary Data Sheet 11.1999
Table 9-11 Motorola Bus Interface Timing
Table 9-10 Motorola Bus Interface Timing
Table 9-4 DC Characteristics (PCI
Table 9-5 PCI Clock Characteristics
Table 9-6 PCI Interface Signal
Table 9-8 Intel Bus Interface Timing
Table 9-9 Intel Bus Interface Timing
4
Table 9-1 Absolute Maximum
PEB 20256 E
PEF 20256 E
DS2
04.2001