PEB20256E-V21 Infineon Technologies, PEB20256E-V21 Datasheet - Page 77

• Manufacturer Part Number: PEB20256E-V21
• Description: IC CONTROLLER INTERFACE 388-BGA
• Manufacturer: Infineon Technologies

Specifications of PEB20256E-V21

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, PPP, Serial, TMA
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 200mA
• Power (watts): 3W
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Circuits: -
• Other names: PEB20256E-V21; PEB20256E-V21IN

occurs in the internal transmit buffer (because of PCI latency e.g.) an abort sequence
with 7 ‘1’s is transmitted and an underrun interrupt is generated. The abort sequence is
also generated if the host CPU resets or aborts a channel during the transmission of a
frame.
An invert option is provided to invert all the data output or data input between serial line
and protocol machines or vice versa.
The following CRC modes are supported:
• 16 bit CRC
• 32 bit CRC
Optionally CRC transfer and check can be disabled.
4.5.2
•
Figure 4-11
Same as HDLC. The handling of the abort sequence differs from that in HDLC mode. If
7E
“1”s. If FF
of 15 “1”s.
The same programmable parameters as in HDLC mode apply to bit synchronous PPP.
4.5.3
This mode uses a frame structure similar to the bit synchronous PPP mode. The frame
begin and end synchronization is performed with the flag character (7E
shared opening and closing flag is supported if programmed in the channel configuration
register. Use of a shared ’0’ bit between two flags is not supported. A 16 or 32 bit CRC
is computed over all service data read from the transmit buffer and appended to the end
of the frame.
The octet synchronous PPP mode uses octet stuffing instead of ‘0’ bit stuffing in order to
replace control characters used by intervening hardware equipment. This allows
transparent transmission and also recognition and removal of spurious characters
inserted by such equipment.
A 32 bit per channel asynchronous control character map (ACCM) specifies characters
in the range 00
the DEL control character (7F
programmable 32 bit register can be selected for character stuffing/destuffing. When a
Data Sheet
H
is programmed as interframe time fill character, the abort sequence consists of 7
0111 1110
Flag
H
Bit Synchronous PPP with HDLC Framing Structure
is programmed as interframe time fill character, the abort sequence consists
Octet Synchronous PPP
Bit Synchronous PPP with HDLC Framing Structure
H
-1F
1111 1111
Address
1+x+x
1+x
H
to be stuffed/destuffed in service data and FCS field. In addition,
5
+x
2
+x
12
0000 0011
Control
+x
4
+x
H
16
5
) and any of 4 ACCM extension characters stored in a
+x
7
+x
Protocol
8/16 bits
8
+x
10
77
+x
Information
11
+x
12
+x
16
Padding
+x
22
+x
Functional Description
23
16/32 bits
+x
FCS
26
+x
32
PEB 20256 E
PEF 20256 E
0111 1110
H
Flag
). Use of a
04.2001