PEB20256E-V21 Infineon Technologies, PEB20256E-V21 Datasheet - Page 49

• Manufacturer Part Number: PEB20256E-V21
• Description: IC CONTROLLER INTERFACE 388-BGA
• Manufacturer: Infineon Technologies

Specifications of PEB20256E-V21

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, PPP, Serial, TMA
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 200mA
• Power (watts): 3W
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Circuits: -
• Other names: PEB20256E-V21; PEB20256E-V21IN

PEB 20256 E
PEF 20256 E
General Overview
independently in transmit and receive direction. In order to avoid transmit underrun
conditions each transmit channel has two control parameters for smoothing the filling/
emptying process (transmit forward threshold, transmit refill threshold). In receive
direction each channel has a receive burst threshold. To avoid unnecessary waste of bus
bandwidth, e.g. in case of transmission errors, the receive buffer provides the capability
to discard frames which are smaller than a programmable threshold.
Data management units
The data management units provide direct data transfer between the system memory
and the internal buffers. Each channel has an associated linked list of descriptors, which
is located in system memory and handled by the data management units. This linked list
is the interface between the system processor and the MUNICH256 for exchange of data
packets. The descriptors and the data packets can be stored arbitrarily in 32 bit address
space of system memory, thus allowing full scatter/gather assembly of packets. In order
to optimize PCI bus utilization, each descriptor is read in one burst and held on-chip
afterwards.
Interrupt controller
Two interrupt controllers manage internal interrupts. Interrupts from the mailbox are
passed in the form of interrupt vectors to an internal interrupt FIFO which can be read
from the local bus. All system, port and channel related interrupt information is passed
to the main interrupt controller which is connected to the PCI system. A programmable
DMA with nine channels stores these interrupts in the form of interrupt vectors in different
interrupt queues in system memory.
PCI interface
The PCI interface unit combines all DMA requests from the internal data management
unit and the interrupt controller and translates them into PCI Rev. 2.1 compliant bus
accesses. The PCI interface optionally includes the function of loading the subsystem
vendor ID and the subsystem ID from an external SPI compliant EEPROM.
Mailbox, internal bridge and global registers
The mailbox is used to exchange data between the PCI attached microprocessor and
the local bus microprocessor and provides a doorbell function between the two
interfaces.
Controlled by an arbiter an internal bridge connects the configuration bus I and the
configuration bus II. It is NOT possible to access the configuration bus I and therefore
the ’HDLC’ registers or the PCI bridge from the local bus.
Data Sheet
49
04.2001