PEB20256E-V21 Infineon Technologies, PEB20256E-V21 Datasheet - Page 84

• Manufacturer Part Number: PEB20256E-V21
• Description: IC CONTROLLER INTERFACE 388-BGA
• Manufacturer: Infineon Technologies

Specifications of PEB20256E-V21

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, PPP, Serial, TMA
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 200mA
• Power (watts): 3W
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Circuits: -
• Other names: PEB20256E-V21; PEB20256E-V21IN

4.7.1.2
•
MB
RBAF
RBEW
RAEW
PB
INFO
Data Sheet
31
15
1
30
11
System Interrupts
B
29
Mailbox
The ’Mailbox’ interrupt vector is generated, in case that the local
microprocessor has written data to the mailbox status register MBE2P0.
The bit field INFO contains a copy of MBE2P0.
Receive Buffer Access Failed
The ’Receive Buffer Access Failed’ interrupt vector is generated, when
the
inaccessibility of the receive buffer. This interrupt is issued as soon as
the programmable threshold stored in register RBAFT is reached. The
actual value of discarded packets is stored in register RBAFC.
Receive Buffer Queue Early Warning
The ’Receive Buffer Queue Early Warning’ interrupt vector is generated,
when
(RBTH.RBTH). This interrupt can be masked via bit CONF1.RBIM.
Receive Buffer Action Queue Early Warning
The ’Receive Buffer Action Queue Early Warning’ interrupt vector is
generated,
(RBTH.RBAQTH) has been exceeded. The receive buffer action queue
stores all requests of the receive buffer to forward data packets to
system memory. This interrupt vector can be masked via bit
CONF1.RBIM.
PCI Access Error
The ’PCI Access Error’ interrupt vector is generated, when system
software tries to read/write internal registers with accesses that do not
enable all byte lanes, e.g. the access is not a full 32 bit access. The bit
field INFO contains the register address which was tried to access.
Contains additional interrupt information data according to the bit, which
is set: See specific interrupt for details.
28
00
protocol
B
the
27
receive
when
26
QUEUE(2:0)
machine
the
buffer
INFO(15:0)
24
84
discarded
receive
0
data
0
threshold
data
packets
0
action
MB
20
Functional Description
has
RBF RBEWRAEW PB
due
19
queue
been
PEB 20256 E
18
to
PEF 20256 E
permanent
17
exceeded
threshold
04.2001
16
0