AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 13
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 13 of 1012
- Download datasheet (16Mb)
3.2.4
3.2.5
32072G–11/2011
JTAG port connections
Nexus OCD AUX port connections
Note:
Table 3-4.
If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-
spective of the GPIO configuration. Three differents OCD trace pin mappings are possible,
depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Tech-
nical Reference Manual.
Table 3-5.
TFBGA144
TFBGA144
K12
L12
J10
J11
A7
B7
A8
A9
K5
H6
MSEO[1]
MSEO[0]
EVTO_N
1. This ball is physically connected to 2 GPIOs. Software must managed carrefully the GPIO con-
EVTI_N
MDO[5]
MDO[4]
MDO[3]
MDO[2]
MDO[1]
MDO[0]
MCKO
Pin
figuration to avoid electrical conflict
JTAG Pinout
Nexus OCD AUX port connections
QFP144
107
108
105
104
QFP144
18
19
13
12
98
99
Table 3-3.Oscillator Pinout
AXS=0
PB05
PA00
PA01
PA03
PA16
PA13
PA12
PB07
PB06
PA10
PA11
VFBGA100
K9
K8
H7
VFBGA100
J8
K5
A5
A6
B7
A7
K6
(1)
Pin name
TDO
TMS
TCK
TDI
AXS=1
PA08
PX56
PX57
PX58
PA24
PA23
PA22
PA07
PX55
PX00
PB06
Pin name
PC02
PC03
PC04
PC05
PC00
PC01
JTAG pin
Oscillator pin
TDO
TMS
TCK
TDI
XOUT32
XOUT0
XOUT1
XIN32
XIN0
XIN1
AXS=2
PX00
PX06
PX05
PX04
PX03
PX02
PX01
PX08
PX07
PB09
PB06
13
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