AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 527
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 527 of 1012
- Download datasheet (16Mb)
• START: Receive Start Selection
• CKG: Receive Clock Gating Selection
• CKI: Receive Clock Inversion
• CKO: Receive Clock Output Mode Selection
• CKS: Receive Clock Selection
32072G–11/2011
START
Others
Others
CKG
CKO
CKS
0
1
2
3
0
1
2
3
4
5
6
7
8
0
1
2
3
0
1
2
CKI affects only the receive clock and not the output clock signal.
1: The data inputs (Data and Frame Sync signals) are sampled on receive clock rising edge. The Frame Sync signal output is
shifted out on receive clock falling edge.
0: The data inputs (Data and Frame Sync signals) are sampled on receive clock falling edge. The Frame Sync signal output is
shifted out on receive clock rising edge.
Selected Receive Clock
Divided clock
TX_CLOCK clock signal
RX_CLOCK pin
Reserved
Continuous, as soon as the receiver is enabled, and immediately after the end of
transfer of the previous data.
Transmit start
Detection of a low level on RX_FRAME_SYNC signal
Detection of a high level on RX_FRAME_SYNC signal
Detection of a falling edge on RX_FRAME_SYNC signal
Detection of a rising edge on RX_FRAME_SYNC signal
Detection of any level change on RX_FRAME_SYNC signal
Detection of any edge on RX_FRAME_SYNC signal
Compare 0
Reserved
None, continuous clock
Receive Clock enabled only if RX_FRAME_SYNC is low
Receive Clock enabled only if RX_FRAME_SYNC is high
Reserved
Receive Clock Output Mode
None
Continuous receive clock
Receive clock only during data transfers
Reserved
Receive Start
Receive Clock Gating
RX_CLOCK pin
Input-only
Output
Output
527
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