AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 851
AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 851 of 1012
- Download datasheet (16Mb)
• CSTOE: Completion Signal Time-out Error
• DTOE: Data Time-out Error
• DCRCE: Data CRC Error
• RTOE: Response Time-out Error
• RENDE: Response End Bit Error
• RCRCE: Response CRC Error
• RDIRE: Response Direction Error
• RINDE: Response Index Error
• TXBUFE: TX Buffer Empty Status
• RXBUFF: RX BUffer Full Status
• CSRCV: CE-ATA Completion Signal Received
• SDIOWAIT: SDIO Read Wait Operation Status
• SDIOIRQB: SDIO Interrupt for Slot B
• SDIOIRQA: SDIO Interrupt for Slot A
• ENDTX: End of RX Buffer
• ENDRX: End of RX Buffer
• NOTBUSY: MCI Not Busy
32072G–11/2011
This bit is set when the completion signal time-out defined by the CSTOR.CSTOCYC field and the CSTOR.CSTOMUL field is
reached.
This bit is cleared when reading the SR register.
This bit is set when the data time-out defined by the DTOR.DTOCYC field and the DTOR.DTOMUL field is reached.
This bit is cleared when reading the SR register.
This bit is set when a CRC16 error is detected in the last data block.
This bit is cleared when reading the SR register.
This bit is set when the response time-out defined by the CMDR.MAXLAT bit is reached.
This bit is cleared when writing the CMDR register.
This bit is set when the end bit of the response is not detected.
This bit is cleared when writing the CMDR register.
This bit is set when a CRC7 error is detected in the response.
This bit is cleared when writing the CMDR register.
This bit is set when the direction bit from card to host in the response is not detected.
This bit is cleared when writing the CMDR register.
This bit is set when a mismatch is detected between the command index sent and the response index received.
This bit is cleared when writing the CMDR register.
This bit is set when the DMA Tx Buffer is empty.
This bit is cleared when the DMA Tx Buffer is not empty.
This bit is set when the DMA Rx Buffer is full.
This bit is cleared when the DMA Rx Buffer is not full.
This bit is set when the device issues a command completion signal on the command line.
This bit is cleared when reading the SR register.
This bit is set when the data bus has entered IO wait state.
This bit is cleared when normal bus operation.
This bit is cleared when reading the SR register.
This bit is set when a SDIO interrupt on Slot B occurs.
This bit is set when a SDIO interrupt on Slot A occurs.
This bit is cleared when reading the SR register.
This bit is set when the DMA Controller transmission is finished.
This bit is cleared when the DMA Controller transmission is not finished.
This bit is set when the DMA Controller reception is finished.
This bit is cleared when the DMA Controller reception is not finished.
This bit must be used only for write operations.
851
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