AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 656
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 656 of 1012
- Download datasheet (16Mb)
32072G–11/2011
•Programming example for multi-block dma transfer : run and link at end of buffer
•Programming example for multi-block dma transfer : load next descriptor now
The idea is to run first a single block transfer followed automatically by a linked list of DMA. The
following sequence may be used:
The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable.
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
nation address until the endpoint is empty or the channel byte length is reached. Once the
endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared.
Once the first DMA channel is completed (i.e : the channel byte length is reached), after one or
multiple processed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a conse-
q u e n c e ,
UDDMAnSTATUS.EOCHBUFFSTA bit is set indicating a end of dma channel. If the UDDMAn-
CONTROL.DMAENDEN bit was set, the last endpoint bank will be properly released even if
there are some residual datas inside, i.e: OUT packet truncation at the end of DMA buffer when
the dma channel byte lenght is not an integral multiple of the endpoint size. Note that the
UDDMAnCONTROL.LDNXTCH bit remains to one indicating that a linked descriptor will be
loaded.
Once the new descriptor is loaded from the UDDMAnNEXTDESC memory address, the UDDM-
AnSTATUS.DESCLDSTA bit is set, and the UDDMAnCONTROL register is updated from the
memory. As a consequence, the UDDMAnSTATUS.CHEN bit is set, and the UDDMAnSTA-
TUS.CHACTIVE is set as soon as the endpoint is ready to be sourced by the DMA (received
OUT data packet).
This sequence is repeated until a last linked descriptor is processed. The last descriptor is
detected according to row 2 as shown in
At the end of the last descriptor, the UDDMAnCONTROL.CHEN bit is cleared. As a conse-
quence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared.
The idea is to directly run first a linked list of DMA. The following sequence may be used: The
following sequence may be used:
• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching
• Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items
• Write the starting destination address in the UDDMAnADDR register.
• Program the UDDMAnNEXTDESC register.
• Program the channel byte length in the UDDMAnCONTROL register.
• Optionnaly set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register.
• Program the UDDMAnCONTROL according to Row 4 as shown in
• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching
for this endpoint in the UECFGn register to handle multiple OUT packet.
: channel next descriptor address, channel destination address and channel control. The last
descriptor should be programmed according to row 2 as shown in
for this endpoint in the UECFGn register to handle multiple OUT packet.
t h e
U D D M A n S T A T U S . C H E N
Figure 26-6 on page
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i s
707.
a l s o
Figure 26-6 on page
Figure 26-6 on page
c l e a r e d ,
a n d
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t h e
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