AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 857
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 857 of 1012
- Download datasheet (16Mb)
30.7.17
Name:
Access Type:
Offset:
Reset Value:
• LSYNC: Synchronize on the last block
• HSMODE: High Speed Mode
• FERRCTRL: Flow Error bit reset control mode
• FIFOMODE: MCI Internal FIFO control mode
32072G–11/2011
31
23
15
7
-
-
-
-
1: The pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall be
different from zero)
0: The pending command is sent at the end of the current data block.
This register needs to configured before sending the data transfer command.
1: The host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall check the
high speed support in the card registers.
0: Default bus timing mode.
1: When an underflow/overflow condition bit is set, reading SR resets the bit.
0: When an underflow/overflow condition bit is set, a new Write/Read command is needed to reset the bit.
1: A write transfer starts as soon as one data is written into the FIFO.
0: A write transfer starts when a sufficient amount of data is written into the FIFO.
When the block length is greater than or equal to 3/4 of the MCI internal FIFO size, then the write transfer starts as soon as half
the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer starts as
soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is written in the
internal FIFO.
Configuration Register
30
22
14
6
-
-
-
-
CFG
Read/Write
0x054
0x00000000
29
21
13
5
-
-
-
-
FERRCTRL
LSYNC
28
20
12
4
-
-
27
19
11
3
-
-
-
-
26
18
10
2
-
-
-
-
25
17
9
1
-
-
-
-
FIFOMODE
HSMODE
24
16
8
0
-
-
857
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