AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 730
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 730 of 1012
- Download datasheet (16Mb)
26.8.3.16
Register Name:
Access Type:
Offset:
Reset Value:
• RSTDT: Reset Data Toggle
• PFREEZE: Pipe Freeze
• PDISHDMA: Pipe Interrupts Disable HDMA Request Enable
• FIFOCON: FIFO Control
• NBUSYBKE: Number of Busy Banks Interrupt Enable
• SHORTPACKETIE: Short Packet Interrupt Enable
32072G–11/2011
PACKETIE
SHORT
31
23
15
7
-
-
-
This bit is set when the RSTDTS bit is written to one. This will reset the Data Toggle to its initial value for the current Pipe.
This bit is cleared when proceed.
This bit is set when the PFREEZES bit is written to one or when the pipe is not configured or when a STALL handshake has
been received on this Pipe or when an error occurs on the Pipe (PERR is one) or when (INRQ+1) In requests have been
processed or when after a Pipe reset (UPRST.PRSTn rising) or a Pipe Enable (UPRST.PEN rising). This will Freeze the Pipe
requests generation.
This bit is cleared when the PFREEZEC bit is written to one. This will enable the Pipe request generation.
See the UECONn.EPDISHDMA bit description.
For OUT and SETUP Pipe:
This bit is set when the current bank is free, at the same time than TXOUTI or TXSTPI.
This bit is cleared when the FIFOCONC bit is written to one. This will send the FIFO data and switch the bank.
For IN Pipe:
This bit is set when a new IN message is stored in the current bank, at the same time than RXINI.
This bit is cleared when the FIFOCONC bit is written to one. This will free the current bank and switch to the next bank.
This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE).
This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interrupt (NBUSYBKE).
This bit is set when the SHORTPACKETES bit is written to one. This will enable the Transmitted IN Data IT
(SHORTPACKETIE).
This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Transmitted IN Data IT
(SHORTPACKETE).
Pipe n Control Register
RXSTALLDE
/CRCERRE
FIFOCON
30
22
14
6
-
-
UPCONn, n in [0..7]
Read-Only
0x05C0 + (n * 0x04)
0x00000000
OVERFIE
29
21
13
5
-
-
-
NBUSYBKE
NAKEDE
28
20
12
4
-
-
PERRE
27
19
11
3
-
-
-
UNDERFIE
TXSTPE/
RSTDT
26
18
10
2
-
-
PFREEZE
TXOUTE
25
17
9
1
-
-
PDISHDMA
RXINE
24
16
8
0
-
-
730
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