AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 574
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 574 of 1012
- Download datasheet (16Mb)
25.6.9.1
25.6.9.2
25.6.9.3
25.6.9.4
25.6.9.5
Figure 25-39. Header Transmission
25.6.9.6
32072G–11/2011
Baud Rate
TXRDY
LINIR
LINIR
Clock
Write
TXD
Receiver and Transmitter Control
Baud Rate Configuration
Modes of operation
Character Transmission and Reception
Header Transmission (Master Node Configuration)
Header Reception (Slave Node Configuration)
ID
13 dominant bits (at 0)
customizable response data lengths, and requires minimal CPU resources. Writing 0xA (master)
or 0xB (slave) to MR.MODE enables this mode.
Changing LIN mode after initial configuration has to be followed by a transceiver software reset
in order to avoid unpredictable behavior.
See Section “25.6.2” on page 552.
The LIN nodes baud rate is configured in the Baud Rate Generator Register (BRGR),
tion “25.6.1.1” on page 549.
See
All LIN frames start with a header sent by the master. As soon as the identifier has been written
to the Identifier Character field in the LIN Identifier Register (LINIR.IDCHR), TXRDY is cleared
and the header is sent. The header consists of a Break, Sync, and Identifier field. TXRDY is set
when the identifier has been transferred into the transmitters shift register.
The Break field consists of 13 dominant bits, the break, and one recessive bit, the break delim-
iter. The Sync field is the character 0x55. The Identifier field contains the Identifier as written to
IDCHR. The identifier parity bits can be generated automatically (see
The USART stays idle until it detects a break field, consisting of at least 11 consecutive domi-
nant bits (zeroes) on the bus. A received break will set the Lin Break bit (CSR.LINBK). The Sync
field is used to synchronize the baud rate (see
Identifier bit (CSR.LINIR) is set when the Identifier has been received. The Identifier parity bits
can be automatically checked (see
and LINIR.
Break Field
”Transmitter Operations” on page
1 recessive bit
Delimiter
Break
(at 1)
Start
Bit
1
Section
0
Synch Byte = 0x55
553, and
1
0
25.6.9.8). Writing a one to RSTSTA will clear LINBK
1
Section
0
”Receiver Operations” on page
1
0
25.6.9.7). IDCHR is updated and the LIN
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Section
25.6.9.8).
560.
Stop
See Sec-
Bit
574
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