AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 898
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 898 of 1012
- Download datasheet (16Mb)
32.5.6
Name:
Access Type:
Offset:
Reset Value:
• URAT: Unspecified Register Access Type:
• URAD: Unspecified Register Access Detection Status
•
•
•
•
32072G–11/2011
Others
URAT
31
23
15
7
-
-
-
0
1
2
3
4
5
Only the last Unspecified Register Access Type is available through the URAT field.
This field is reset to 0 when SWRST bit in the Control Register is written to one.
This bit is set when at least one unspecified register access has been detected since the last software reset.
This bit is cleared when SWRST bit in the Control Register is set to one.
Interrupt Status Register
Description
The IDATAnR register during the data processing in DMA mode.
The ODATAnR register read during the data processing.
The MR register written during the data processing.
The ODATAnR register read during the sub-keys generation.
The MR register written during the sub-keys generation.
Write-only register read access.
Reserved
30
22
14
6
-
-
-
ISR
Read-only
0x1C
0x0000001E
URAT
29
21
13
5
-
-
-
28
20
12
4
-
-
-
27
19
11
3
-
-
-
-
26
18
10
2
-
-
-
-
25
17
9
1
-
-
-
-
DATRDY
URAD
24
16
8
0
-
-
898
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