AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 165
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 165 of 1012
- Download datasheet (16Mb)
14.5
14.5.1
14.5.2
14.5.3
32072G–11/2011
Product Dependencies
I/O Lines
Power Management
Clocks
In order to use this module, other parts of the system must be configured correctly, as described
below.
The pins used for interfacing the compliant external devices may be multiplexed with I/O Con-
troller lines. The user must first configure the I/O Controller to assign the EBI pins to their
peripheral functions.
To prevent bus errors EBI operation must be terminated before entering sleep mode.
A number of clocks can be selected as source for the EBI. The selected clock must be enabled
by the Power Manager.
The following clock sources are available:
• CLK_EBI
• CLK_SDRAMC
• CLK_SMC
Pin Name
ADDR[17]
NCS[4]
NCS[5]
NCS[2]
NCS[3]
NWE0
NWE1
NRD
NWE1-NBS1/
NWE0-NWE
NANDCS[0]
NANDCS[1]
ADDR[17]
CFNIORD
Alternate
CFCS[0]
CFCS[1]
CFNWE
CFNOE
NCS[4]
NCS[5]
NCS[2]
NCS[3]
DQM1/
Name
NRD
BA1
SMC/NAND Flash/SmartMedia shared lines
SDRAMC/SMC/CompactFlash shared lines
SMC/CompactFlash shared lines
SDRAMC Bank 1
SMCAddress Bus Line 17
SMC Read Signal
CompactFlash CFNOE
SMC Write Enable10 or Write enable
CompactFlash CFNWE
SMC Chip Select Line 4
CompactFlash Chip Select Line 0
SMC Chip Select Line 5
CompactFlash Chip Select Line 1
SMC Chip Select Line 2
NANDFlash/SmartMedia Chip Select Line
0
SMC Chip Select Line 3
NANDFlash/SmartMedia Chip Select Line
1
SDRAMC DQM1
SMC Write Enable1 or Byte Select 1
CompactFlash CFNIORD
Pin Description
Output
Output
Output
Output
Output
Output
Output
Output
Type
Active
Level
Low
Low
Low
Low
Low
Low
165
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