AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 419
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 419 of 1012
- Download datasheet (16Mb)
• WDRBT: Wait Data Read Before Transfer
• MODFDIS: Mode Fault Detection
• PCSDEC: Chip Select Decode
• PS: Peripheral Select
• MSTR: Master/Slave Mode
32072G–11/2011
0: The FIFO is not used in reception (only one character can be stored in the SPI).
1: In master mode, a transfer can start only if the RDR register is empty, i.e. does not contain any unread data. This mode
prevents overrun error in reception.
0: No Effect. In master mode, a transfer can be initiated whatever the state of the RDR register is.
1: Mode fault detection is disabled. If the I/O controller does not have open-drain capability, mode fault detection must be
disabled for proper operation of the SPI.
0: Mode fault detection is enabled.
0: The chip selects are directly connected to a peripheral device.
1: The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The CSRn registers define the characteristics of the 15 chip selects according to the following rules:
CSR0 defines peripheral chip select signals 0 to 3.
CSR1 defines peripheral chip select signals 4 to 7.
CSR2 defines peripheral chip select signals 8 to 11.
CSR3 defines peripheral chip select signals 12 to 14.
1: Variable Peripheral Select.
0: Fixed Peripheral Select.
1: SPI is in master mode.
0: SPI is in slave mode.
419
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