AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 869
AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 869 of 1012
- Download datasheet (16Mb)
31.6.6
31.7
Table 31-2.
32072G–11/2011
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
User Interface
Offset
OCD mode
MSI Register Memory Map
Register
Command register
Data register
Status register
System register
Interrupt Status register
Interrupt Status Clear register
Interrupt Enable register
Interrupt Disable register
Interrupt Mask register
Version register
the interrupt source, even if the interrupt is masked, can be read in ISR.
DRQ interrupt request is cleared by reading (reception) or writing (transmission) FIFO, other
interrupt requests are cleared by writing 1 to the corresponding bit in Interrupt Status Clear Reg-
ister (ISCR).
There is no OCD mode for MSI.
CMD
DAT
SR
SYS
ISR
ISCR
IER
IDR
IMR
VERSION
Name
Read/Write
Read/Write
Read Only
Read/Write
Read Only
Write Only
Write Only
Write Only
Read Only
Read Only
Access
0x00000000
0x4C004C00
0x00001020
0x00004015
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000210
Reset State
869
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