AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 336
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 336 of 1012
- Download datasheet (16Mb)
19.10.1.4
32072G–11/2011
Multi-block Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row7)
Figure 19-12. DMA Transfer Flow for Source and Destination Address Auto-reloaded
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of linked list items (otherwise known as block descriptors) in memory.
Write the control information in the LLI.CTLx register location of the block descriptor for
each LLI in memory for channel x. For example, in the register you can program the
following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_TR_WIDTH field.
– ii. Transfer width for the destination in the DST_TR_WIDTH field.
– iii. Source master layer in the SMS field where source resides.
– iv. Destination master layer in the DMS field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SINC field.
nation) and flow control peripheral by programming the TT_FC of the CTLx
register.
DMAC transfer Complete
interrupt generated here
Channel Disabled by
hardware
Block Complete interrupt
generated here
yes
interrupt cleared by software
Reload SARx, DARx, CTLx
DMAC State Machine Table?
Stall until block complete
Channel Enabled by
MASKBLOCK[x]=1?
Is DMAC in Row1 of
CTLx.INT_EN=1
Block Transfer
software
&&
yes
no
no
336
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