AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 805
AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 805 of 1012
- Download datasheet (16Mb)
29.4
29.4.1
29.5
32072G–11/2011
Product Dependencies
Functional Description
Clocks
In order to use this module, other parts of the system must be configured correctly, as described
below.
The clock for the BUSMON bus interface (CLK_BUSMON) is generated by the Power Manager.
This clock is enabled at reset and can be disabled in the Power Manager. It is recommended to
disable the BUSMON before disabling the clock, to avoid freezing the BUSMON in an undefined
state.
Three different parameters can be measured by each channel:
These measurements can be extracted by software and used to generate indicators for bus
latency, bus load and maximum bus latency.
Each of the counters have a fixed width, and may therefore overflow. When overflow is encoun-
tered in either the Channel n Data Cycles (DATAn) register or the Channel n Stall Cycles
(STALLn) register of a channel, all registers in the channel are reset. This behavior is altered if
the Channel n Overflow Freeze (CHnOF) bit is set in the Control (CONTROL) register. If this bit
is written to one, the channel registers are frozen when either DATAn or STALLn reaches its
maximum value. This simplifies one-shot readout of the counter values.
The registers can also be manually reset by writing to the CONTROL register. The Channeln
Max Initiation Latency (LATn) register is saturating, when its max count is reached, it will be set
to its maximum value. The LATn register is reset whenever DATAn and STALLn are reset.
A counter must manually be enabled by writing to the CONTROL register.
• The number of data transfer cycles since last channel reset
• The number of stall cycles since last channel reset
• The maximum continuous number of stall cycles since last channel reset (This approximates
the max latency in the transfers.)
805
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