AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 571
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 571 of 1012
- Download datasheet (16Mb)
25.6.8
25.6.8.1
25.6.8.2
25.6.8.3
32072G–11/2011
SPI Mode
Modes of Operation
Baud Rate
Data Transfer
The USART features a Serial Peripheral Interface (SPI) link compliant mode, supporting syn-
chronous, full-duplex communication, in both master and slave mode. Writing 0xE (master) or
0xF (slave) to MR.MODE will enable this mode. A SPI in master mode controls the data flow to
and from the other SPI devices, who are in slave mode. It is possible to let devices take turns
being masters (aka multi-master protocol), and one master may shift data simultaneously into
several slaves, but only one slave may respond at a time. A slave is selected when its slave
select (NSS) signal has been raised by the master. The USART can only generate one NSS sig-
nal, and it is possible to use standard I/O lines to address more than one slave.
The SPI system consists of two data lines and two control lines:
Changing SPI mode after initial configuration has to be followed by a transceiver software reset
in order to avoid unpredictable behavior.
The baud rate generator operates as described in
on page
In SPI Master Mode:
In SPI Slave Mode:
• Master Out Slave In (MOSI): This line supplies the data shifted from master to slave. In
• Master In Slave Out (MISO): This line supplies the data shifted from slave to master. In
• Serial Clock (CLK): This is controlled by the master. One period per bit transmission. In both
• Slave Select (NSS): This control line allows the master to select or deselect a slave. In
• The Clock Selection field (MR.USCLKS) must not equal 0x3 (external clock, CLK).
• The Clock Output Select bit (MR.CLKO) must be one.
• The BRGR.CD field must be at least 0x4.
• If USCLKS is one (internal divided clock, CLK_USART/DIV), the value in CD has to be even,
• CLK frequency must be at least four times lower than the system clock.
• Up to nine data bits are successively shifted out on the TXD pin at each edge. There are no
master mode this is connected to TXD, and in slave mode to RXD.
master mode this is connected to RXD, and in slave mode to TXD.
modes this is connected to CLK.
master mode this is connected to RTS, and in slave mode to CTS.
ensuring a 50:50 duty cycle. CD can be odd if USCLKS is zero (internal clock, CLK_USART).
start, parity, or stop bits, and MSB is always sent first. The SPI Clock Polarity (MR.CPOL),
and SPI Clock Phase (MR.CPHA) bits configure CLK by selecting the edges upon which bits
are shifted and sampled, resulting in four non-interoperable protocol modes see
A master/slave pair must use the same configuration, and the master must be reconfigured if
it is to communicate with slaves using different configurations. See
551, with the following requirements:
”Baud Rate in Synchronous and SPI Mode”
Figures 25-37 and
Table
25-13.
25-38.
571
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