AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 875
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 875 of 1012
- Download datasheet (16Mb)
31.7.4
Name :
Access Type :
Offset :
Reset Value :
•
•
•
•
•
•
•
32072G–11/2011
CLKDIV : Clock Division.
RST : Reset. When RST is written, internal synchronous reset is performed.
SRAC : Serial Access Mode. The SRAC cannot be changed during protocol execution.
NOCRC : No CRC computation.
FCLR : FIFO clear.
FDIR : FIFO direction.
REI : Rising Edge Input. When setting parallel mode, set REI=0. This setting cannot be changed during protocol execution.
RST
Write this field to change SCLK frequency = CLK_MSI / (2*(CLKDIV+1)).
0 : This bit is cleared to 0 after the internal reset is completed.
1 : Writing a 1 starts reset operation.
0 : Write this bit to 0 to set parallel mode.
1 : Write this bit to 1 to set serial mode.
0 : Write 0 to enable CRC output. During read protocol, the CRC check is performed as usual regardless of NOCRC.
1 : Write 1 to disable CRC output. When NOCRC=1, the write protocol is executed without adding the CRC data.
Write 1 to initialize FIFO data. This bit is cleared after the FIFO is initialized.
0 : Write 0 to set the FIFO direction to transmit.
1 : Write 1 to set the FIFO direction to receive.
0 : Write 0 to sample data at the falling edge of SCLK.
31
23
15
7
-
-
System register
SRAC
30
22
14
SYS
Read/Write
0x0C
0x00004015
6
-
-
29
21
13
5
-
-
-
NOCRC
REI
28
20
12
4
-
CLKDIV
REO
27
19
11
3
-
-
26
18
10
2
-
-
FCLR
BSY
25
17
9
1
-
FDIR
24
16
8
0
-
875
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