ATmega1280 Atmel Corporation, ATmega1280 Datasheet - Page 158

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ATmega1280

Manufacturer Part Number
ATmega1280
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega1280

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
86
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
1
Uart
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
16
Input Capture Channels
4
Pwm Channels
15
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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17.11 Register Description
17.11.1
17.11.2
17.11.3
17.11.4
2549N–AVR–05/11
TCCR1A – Timer/Counter 1 Control Register A
TCCR3A – Timer/Counter 3 Control Register A
TCCR4A – Timer/Counter 4 Control Register A
TCCR5A – Timer/Counter 5 Control Register A
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB,
and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the
OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func-
tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,
the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-
ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or
OCnC pin must be set in order to enable the output driver.
When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is
dependent of the WGMn3:0 bits setting.
tionality when the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).
Bit
(0x80)
Read/Write
Initial Value
Bit
(0x90)
Read/Write
Initial Value
Bit
(0xA0)
Read/Write
Initial Value
Bit
(0x120)
Read/Write
Initial Value
Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
COM1A1
COM3A1
COM4A1
COM5A1
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
COM1A0
COM3A0
COM4A0
COM5A0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
ATmega640/1280/1281/2560/2561
COM1B1
COM3B1
COM4B1
COM5B1
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
Table 17-3 on page 159
COM1B0
COM3B0
COM4B0
COM5B0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
COM1C1
COM3C1
COM4C1
COM5C1
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
COM1C0
COM3C0
COM4C0
COM5C0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
shows the COMnx1:0 bit func-
WGM11
WGM31
WGM41
WGM51
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
WGM10
WGM30
WGM40
WGM50
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TCCR1A
TCCR3A
TCCR4A
TCCR5A
158

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