ATmega1280 Atmel Corporation, ATmega1280 Datasheet - Page 81

• Manufacturer Part Number: ATmega1280
• Manufacturer: Atmel Corporation

Specifications of ATmega1280

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 86
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 16
• Input Capture Channels: 4
• Pwm Channels: 15
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

2549N–AVR–05/11
Table 13-7
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source.
Table 13-7.
Table 13-8.
DIEOE
DIEOE
Signal
DIEOV
Signal
DIEOV
PUOE
DDOE
DDOV
PUOE
DDOE
DDOV
Name
PUOV
PVOE
PVOV
Name
PUOV
PVOE
PVOV
AIO
AIO
DI
DI
Figure 13-5 on page
and
SPI SLAVE OUTPUT
OC0/OC1C ENABLE
PB7/OC0A/OC1C
SPI MSTR INPUT
Overriding Signals for Alternate Functions in PB7:PB4
Overriding Signals for Alternate Functions in PB3:PB0
PCINT3 • PCIE0
PCINT7 • PCIE0
PORTB3 • PUD
PCINT3 INPUT
PCINT7 INPUT
Table 13-8
SPE • MSTR
SPE • MSTR
SPE • MSTR
OC0/OC1C
PB3/MISO
0
1
–
0
0
0
0
1
–
relate the alternate functions of Port B to the overriding signals
76. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
ATmega640/1280/1281/2560/2561
SPI MSTR OUTPUT
PCINT6 • PCIE0
SPI SLAVE INPUT
OC1B ENABLE
PCINT6 INPUT
PCINT2 • PCIE0
PORTB2 • PUD
PCINT2 INPUT
PB6/OC1B
SPE • MSTR
SPE • MSTR
SPE • MSTR
PB2/MOSI
OC1B
0
0
0
0
1
–
0
1
–
PCINT5 • PCIE0
OC1A ENABLE
PCINT5 INPUT
PCINT1 • PCIE0
PB5/OC1A
PORTB1 • PUD
PCINT1 INPUT
SCK OUTPUT
SPE • MSTR
SPE • MSTR
SPE • MSTR
SCK INPUT
OC1A
PB1/SCK
0
0
0
0
1
–
0
1
–
PCINT4 • PCIE0
OC2A ENABLE
PCINT4 INPUT
PCINT0 • PCIE0
PORTB0 • PUD
PCINT0 INPUT
SPE • MSTR
SPE • MSTR
PB4/OC2A
PB0/SS
OC2A
SPI SS
0
0
0
0
1
–
0
0
1
–
0
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