ATmega1280 Atmel Corporation, ATmega1280 Datasheet - Page 218

• Manufacturer Part Number: ATmega1280
• Manufacturer: Atmel Corporation

Specifications of ATmega1280

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 86
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 16
• Input Capture Channels: 4
• Pwm Channels: 15
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.6.6
22.6.7
22.7
22.7.1
2549N–AVR–05/11
Asynchronous Data Reception
Disabling the Receiver
Flushing the Receive Buffer
Asynchronous Clock Recovery
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the Receiver
will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be
flushed when the Receiver is disabled. Remaining data in the buffer will be lost.
The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be
emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag
is cleared. The following code example shows how to flush the receive buffer.
Note:
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
The clock recovery logic synchronizes internal clock to the incoming serial frames.
on page 219
rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed
mode. The horizontal arrows illustrate the synchronization variation due to the sampling pro-
cess. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of
operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no com-
munication activity).
Assembly Code Example
C Code Example
USART_Flush:
void USART_Flush( void )
{
}
sbis UCSRnA, RXCn
ret
in
rjmp USART_Flush
unsigned char dummy;
while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;
1. See “About Code Examples” on page 11.
illustrates the sampling process of the start bit of an incoming frame. The sample
r16, UDRn
(1)
(1)
ATmega640/1280/1281/2560/2561
Figure 22-5
218