ATmega1280 Atmel Corporation, ATmega1280 Datasheet - Page 21

• Manufacturer Part Number: ATmega1280
• Manufacturer: Atmel Corporation

Specifications of ATmega1280

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 86
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 16
• Input Capture Channels: 4
• Pwm Channels: 15
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8. AVR Memories
8.1
8.2
2549N–AVR–05/11
In-System Reprogrammable Flash Program Memory
SRAM Data Memory
This section describes the different memories in the ATmega640/1280/1281/2560/2561. The
AVR architecture has two main memory spaces, the Data Memory and the Program Memory
space. In addition, the ATmega640/1280/1281/2560/2561 features an EEPROM Memory for
data storage. All three memory spaces are linear and regular.
The ATmega640/1280/1281/2560/2561 contains 64K/128K/256K bytes On-chip In-System
Reprogrammable Flash memory for program storage, see
are 16 bit or 32 bit wide, the Flash is organized as 32K/64K/128K × 16. For software security,
the Flash Program memory space is divided into two sections, Boot Program section and Appli-
cation Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega640/1280/1281/2560/2561 Program Counter (PC) is 15/16/17 bits wide, thus addressing
the 32K/64K/128K program memory locations. The operation of Boot Program section and asso-
ciated Boot Lock bits for software protection are described in detail in
Read-While-Write Self-Programming” on page
tains a detailed description on Flash data serial downloading using the SPI pins or the JTAG
interface.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description and ELPM - Extended Load Program Memory
instruction description).
Timing diagrams for instruction fetch and execution are presented in
ing” on page
Figure 8-1.
Figure 8-2 on page 23
organized.
The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units
than can be supported within the 64 location reserved in the Opcode for the IN and OUT instruc-
tions. For the Extended I/O space from $060 - $1FF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
The first 4,608/8,704 Data Memory locations address both the Register File, the I/O Memory,
Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register
file, the next 64 location the standard I/O Memory, then 416 locations of Extended I/O memory
and the next 8,192 locations address the internal data SRAM.
0x7FFF/0xFFFF/0x1FFFF
Address (HEX)
17.
Program Flash Memory Map
shows how the ATmega640/1280/1281/2560/2561 SRAM Memory is
0
ATmega640/1280/1281/2560/2561
Application Flash Section
Boot Flash Section
317.
“Memory Programming” on page 335
Figure
8-1. Since all AVR instructions
“Instruction Execution Tim-
“Boot Loader Support –
con-
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