ATmega1280 Atmel Corporation, ATmega1280 Datasheet - Page 278

• Manufacturer Part Number: ATmega1280
• Manufacturer: Atmel Corporation

Specifications of ATmega1280

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 86
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 16
• Input Capture Channels: 4
• Pwm Channels: 15
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.4
2549N–AVR–05/11
Prescaling and Conversion Timing
Figure 26-2. ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-
stantly sampling and updating the ADC Data Register. The first conversion must be started by
writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.
Figure 26-3. ADC Prescaler
By default, the successive approximation circuitry requires an input clock frequency between
50kHz and 200kHz. If a lower resolution than 10 bits is needed, the input clock frequency to the
ADC can be as high as 1000kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA.
ADSC
SOURCE n
ADIF
SOURCE 1
.
.
.
.
ADEN
START
ADTS[2:0]
ADPS0
ADPS1
ADPS2
CK
ATmega640/1280/1281/2560/2561
DETECTOR
EDGE
Reset
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
START
CONVERSION
PRESCALER
LOGIC
CLK
ADC
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