ATmega1280 Atmel Corporation, ATmega1280 Datasheet - Page 37

• Manufacturer Part Number: ATmega1280
• Manufacturer: Atmel Corporation

Specifications of ATmega1280

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 86
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 16
• Input Capture Channels: 4
• Pwm Channels: 15
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.3
9.3.1
9.3.2
9.3.3
9.4
9.4.1
2549N–AVR–05/11
General Purpose registers
External Memory registers
GPIOR2 – General Purpose I/O Register 2
GPIOR1 – General Purpose I/O Register 1
GPIOR0 – General Purpose I/O Register 0
XMCRA – External Memory Control Register A
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct
address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,
ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin
direction settings in the respective data direction registers. Writing SRE to zero, disables the
External Memory Interface and the normal pin and data direction settings are used.
• Bit 6:4 – SRL2:0: Wait-state Sector Limit
It is possible to configure different wait-states for different External Memory addresses. The
external memory address space can be divided in two sectors that have separate wait-state bits.
The SRL2, SRL1, and SRL0 bits select the split of the sectors, see
Bit
0x2B (0x4B)
Read/Write
Initial Value
Bit
0x2A (0x4A)
Read/Write
Initial Value
Bit
0x1E (0x3E)
Read/Write
Initial Value
Bit
“(0x74)”
Read/Write
Initial Value
MSB
MSB
MSB
R/W
R/W
R/W
SRE
R/W
7
0
7
0
7
0
7
0
SRL2
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
ATmega640/1280/1281/2560/2561
SRL1
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
SRL0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
SRW11
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
SRW10
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
Table 9-2 on page 38
SRW01
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
SRW00
LSB
LSB
LSB
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
GPIOR2
GPIOR1
GPIOR0
XMCRA
and
37