ATmega1280 Atmel Corporation, ATmega1280 Datasheet - Page 233

• Manufacturer Part Number: ATmega1280
• Manufacturer: Atmel Corporation

Specifications of ATmega1280

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 86
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 16
• Input Capture Channels: 4
• Pwm Channels: 15
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.2.1
23.3
2549N–AVR–05/11
SPI Data Modes and Timing
Clock Generation
A comparison of the USART in MSPIM mode and the SPI pins is shown in
240.
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For
USART MSPIM mode of operation only internal clock generation (that is, master operation) is
supported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to
one (that is, as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn
should be set up before the USART in MSPIM is enabled (that is, TXENn and RXENn bit set to
one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous mas-
ter mode. The baud rate or UBRRn setting can therefore be calculated using the same
equations, see
Table 23-1.
Note:
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in
the XCKn signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and
UCPHAn functionality is summarized in
these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
Table 23-2.
Operating Mode
Synchronous Master
mode
UCPOLn
BAUD
f
UBRRn
OSC
0
0
1
1
1. The baud rate is defined to be the transfer rate in bit per second (bps).
Figure 23-1 on page
Equations for Calculating Baud Rate Register Setting
UCPOLn and UCPHAn Functionality-
Table
UCPHAn
23-1.
Baud rate (in bits per second, bps).
System Oscillator clock frequency.
Contents of the UBRRnH and UBRRnL Registers, (0-4095).
0
1
0
1
Equation for Calculating Baud
BAUD
234. Data bits are shifted out and latched in on opposite edges of
ATmega640/1280/1281/2560/2561
=
SPI Mode
Rate
-------------------------------------- -
2 UBRRn
(
0
1
2
3
(1)
f
OSC
Table
+
23-2. Note that changing the setting of any of
1
)
Sample (Rising)
Sample (Falling)
Leading Edge
Setup (Rising)
Setup (Falling)
Equation for Calculating
UBRRn
UBRRn Value
=
------------------- - 1
2BAUD
f
OSC
Table 23-4 on page
Sample (Falling)
Sample (Rising)
Setup (Falling)
Setup (Rising)
Trailing Edge
–
233